目录
第51题:Truth tables
module top_module
(
input x3,
input x2,
input x1, // three inputs
output f // one output
);
assign f = x3&x1 | (~x3)&x2;
endmodule
第52题:Two-bit equality
module top_module
(
input [1:0] A,
input [1:0] B,
output z
);
assign z = (A == B);
endmodule
第53题:Simple circuit A
module top_module
(
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
第54题:Simple circuit B
module top_module
(
input x,
input y,
output z
);
assign z = ~(x^y);
endmodule
第55题:Combine circuits A and B
module top_module
(
input x,
input y,
output z
);
wire [1:0] za_o;
wire [1:0] zb_o;
assign z = (za_o[0] | zb_o[0]) ^ (za_o[1] & zb_o[1]);
mt2015_q4a a_inst1
(
.x(x),
.y(y),
.z(za_o[0])
);
mt2015_q4a a_inst2
(
.x(x),
.y(y),
.z(za_o[1])
);
mt2015_q4b b_inst1
(
.x(x),
.y(y),
.z(zb_o[0])
);
mt2015_q4b b_inst2
(
.x(x),
.y(y),
.z(zb_o[1])
);
endmodule
module mt2015_q4a
(
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
module mt2015_q4b
(
input x,
input y,
output z
);
assign z = ~(x^y);
endmodule
第56题:Ring or vibrate?
module top_module
(
input ring ,
input vibrate_mode,
output ringer , // Make sound
output motor // Vibrate
);
assign ringer = ring&(~vibrate_mode) ? 1 : 0;
assign motor = ring&vibrate_mode ? 1 : 0;
endmodule
第57题:Thermostat
module top_module
(
input too_cold,
input too_hot ,
input mode ,
input fan_on ,
output heater ,
output aircon ,
output fan
);
assign heater = too_cold&mode ? 1 : 0;
assign aircon = too_hot&(~mode) ? 1 : 0;
assign fan = fan_on | heater | aircon;
endmodule
第58题:3-bit population count
module top_module
(
input [2:0] in ,
output [1:0] out
);
integer i;
always@(*)
begin
out = 0;
for(i = 0;i < 3; i = i + 1)
out = out + in[i];
end
endmodule
第59题:Gates and vectors
module top_module
(
input [3:0] in ,
output [2:0] out_both ,
output [3:1] out_any ,
output [3:0] out_different
);
assign out_both = in[2:0] & in [3:1];
assign out_any = in[2:0] | in [3:1];
assign out_different = in ^ {in[0],in [3:1]};
endmodule
第60题:Even longer vectors
module top_module
(
input [99:0] in ,
output [98:0] out_both ,
output [99:1] out_any ,
output [99:0] out_different
);
assign out_both = in[98:0] & in [99:1];
assign out_any = in[98:0] | in [99:1];
assign out_different = in ^ {in[0],in [99:1]};
endmodule