【学习笔记】用uart控制vga

        工程目的，用uart控制vga。（简单提升了一下上一个工程）

        功能： 当输入A时才能开启数据往vga的ram中传输数据，并且uart不能控制vga开关状态。当计数到数据量最大值时，uart才能正常控制vga开关状态。当输入B时，将vga开启，正常显示（当先输入B再输入A一边更新vga图像数据一边图像显示）。当输入C时，将vga关闭。（A、B和C为16位数据）
              总体框图：（实际编写全部模块放顶层模块，这样画只是为了方便观看）

 

module uart_ctrl_vga(
	input		wire	clk_sys			,
	input		wire	rst_n_sys		,
	input		wire	rx					,	

	output	wire	[7:0]rgb		,
	output	wire	hsync			,
	output	wire	vsync			
);

//output uart_rx
	wire	[7:0]uart_po_data	;
	wire	uart_po_flag		;

//output ctrl
	wire	[15:0]	ram_addr	;
	wire	[7:0]	ctrl_po_data;
	wire	ctrl_po_flag		;
	wire	vga_on_off			;	

//output clk_divide
	wire	clk_vga				;

//output	vga_pic
	wire	[7:0]pix_data		;
	
//output	vga_ctrl			
	wire	[9:0]pix_x	;
	wire	[9:0]pix_y	;


uart_rx  uart_inst(
	.clk_sys			(clk_sys)	,
	.rst_n_sys		(rst_n_sys)	,
	.rx				(rx)			,
		
	.po_data	(uart_po_data),
	.po_flag			(uart_po_flag)
	);
	

ctrl		ctrl_inst(	
	.clk_sys				(clk_sys)		,
	.rst_n_sys			(rst_n_sys)		,
	.uart_po_data		(uart_po_data)	,
	.uart_po_flag		(uart_po_flag)	,
	
	.ram_addr			(ram_addr)		,
	.ctrl_po_data		(ctrl_po_data)	,
	.ctrl_po_flag		(ctrl_po_flag)	,
	.vga_on_off			(vga_on_off)	
);
	
clk_divide	clk_divide_inst(
	.clk_sys		(clk_sys),
	.rst_n_sys	(rst_n_sys),

	.clk_vga		(clk_vga)	

);
	

vga_pic	vga_pic_inst(
	.clk_vga		(clk_vga)		,
	.rst_n_sys	(rst_n_sys)		,
	.pix_x		(pix_x)			,
	.pix_y		(pix_y)			,
	.clk_sys		(clk_sys)		,
	.po_data		(ctrl_po_data)	,
	.po_flag		(ctrl_po_flag)	,
	.vga_on_off	(vga_on_off)	,
	.ram_addr	(ram_addr)		,

	.pix_data	(pix_data)	

);
	
vga_ctrl	vga_ctrl_inst(
	.clk_vga		(clk_vga)	,
	.rst_n_sys	(rst_n_sys)	,
	.pix_data	(pix_data)	,
	.vga_on_off	(vga_on_off),

	.rgb			(rgb)		,
	.pix_x		(pix_x)	,
	.pix_y		(pix_y)	,
	.hsync		(hsync)	,
	.vsync		(vsync)	
);


	
endmodule

 ctrl模块：

module ctrl(
	input	wire 	clk_sys					,
	input	wire	rst_n_sys				,
	input	wire	[7:0]	uart_po_data	,
	input	wire	uart_po_flag			,
	
	output	reg	[15:0]	ram_addr	,
	output	reg	[7:0]	ctrl_po_data,
	output	reg	ctrl_po_flag		,
	output	reg	vga_on_off			
);
	reg	[15:0]	ctrl_reg	;
	reg	[15:0]	flag_reg	;
	reg	addr_flag			;
	reg	addr_en				;
	
	parameter	A=16'd16351,
					B=16'd50408,
					C=16'd6036;

	parameter	addr_max='d2_500;
	
always@(posedge clk_sys	or negedge rst_n_sys)
	if(!rst_n_sys)
		ctrl_reg<=0												;	
	else	if(addr_en==1)								
		ctrl_reg<=ctrl_reg									;
	else	if(uart_po_flag==1)
		ctrl_reg<={ctrl_reg[7:0],uart_po_data[7:0]}	;
	else
		ctrl_reg<=ctrl_reg									;

always@(posedge clk_sys	or negedge rst_n_sys)
	if(!rst_n_sys)
		flag_reg<=0				;	
	else
		flag_reg<=ctrl_reg	;
		
always@(posedge clk_sys or negedge rst_n_sys)
	if(!rst_n_sys)
		addr_flag<=0	;
	else if(ctrl_reg==A && ctrl_reg!=flag_reg)
		addr_flag<=1	;
	else
		addr_flag<=0	;
	
always@(posedge clk_sys or negedge rst_n_sys)
	if(!rst_n_sys)
		addr_en<=0			;
	else	if(addr_flag)
		addr_en<=1			;
	else	if(ram_addr==addr_max)
		addr_en<=0			;
	else
		addr_en<=addr_en	;
			
always@(posedge clk_sys or negedge rst_n_sys)
	if(!rst_n_sys)
		ram_addr<=0				;
	else if(ram_addr==addr_max)
		ram_addr<=0				;
	else if(addr_en==1 && ctrl_po_flag==1)
		ram_addr<=ram_addr+1'b1	;
	else
		ram_addr<=ram_addr	;
		
always@(posedge clk_sys or negedge rst_n_sys)
	if(!rst_n_sys)begin
		ctrl_po_data<=0		;
		ctrl_po_flag<=0		;
		end
	else	if(addr_en)begin
		ctrl_po_data<=uart_po_data;
		ctrl_po_flag<=uart_po_flag;
		end
	else	begin
		ctrl_po_data<=0		;
		ctrl_po_flag<=0		;
		end
		
always@(posedge clk_sys or negedge rst_n_sys)
	if(!rst_n_sys)
		vga_on_off<=0				;
	else if(addr_en )
		vga_on_off<=vga_on_off	;
	else if(ctrl_reg==B)
		vga_on_off<=1				;
	else if(ctrl_reg==C)
		vga_on_off<=0				;
	else
		vga_on_off<=vga_on_off	;
	
endmodule	

vag_ctrl模块：

module	vga_ctrl(
	input	wire	clk_vga			,
	input	wire	rst_n_sys		,
	input	wire	[7:0]pix_data	,
	input	wire	vga_on_off		,
	
	output	reg	[7:0]rgb		,
	output	wire	[9:0]pix_x	,
	output	wire	[9:0]pix_y	,
	output	reg	hsync			,
	output	reg	vsync			
);

reg	[9:0]cnt_hsync	;
reg	[9:0]cnt_vsync	;
reg	rgb_vaild		;


always@(posedge clk_vga or negedge rst_n_sys	)
	if(~rst_n_sys)
		cnt_hsync<=10'd0				;
	else 	if(~vga_on_off)		
		cnt_hsync<=10'd0				;
	else if(cnt_hsync==10'd799)
		cnt_hsync<=10'd0				;
	else	
		cnt_hsync<=1'b1+cnt_hsync	;

always@(posedge clk_vga or negedge rst_n_sys	)
	if(~rst_n_sys)
		cnt_vsync<=10'd0				;
	else 	if(~vga_on_off)		
		cnt_vsync<=10'd0				;
	else	if(cnt_vsync==10'd524 && cnt_hsync==10'd799)
		cnt_vsync<=10'd0				;
	else	if(cnt_hsync==10'd799)
		cnt_vsync<=cnt_vsync+1'b1	;
	else
		cnt_vsync<=cnt_vsync			;
		
always@(posedge clk_vga or negedge rst_n_sys	)
	if(~rst_n_sys)
		rgb_vaild<=1'b0;
	else 	if(~vga_on_off)		
		rgb_vaild<=1'b0;
	else	if(cnt_hsync>=10'd143 && cnt_hsync<10'd783 && cnt_vsync>=10'd35 && cnt_vsync<=10'd514)
		rgb_vaild<=1'b1				;
	else
		rgb_vaild<=1'b0;

assign		pix_x=(cnt_hsync>=10'd143 && cnt_hsync<10'd783 && cnt_vsync>=10'd35 && cnt_vsync<=10'd514)?cnt_hsync-10'd143:10'hff	;
assign		pix_y=(cnt_hsync>=10'd143 && cnt_hsync<10'd783 && cnt_vsync>=10'd35 && cnt_vsync<=10'd514)?cnt_vsync-10'd35	:10'hff		;
	
always@(posedge clk_vga or negedge rst_n_sys	)
	if(~rst_n_sys)
		hsync<=1'b0		;
	else 	if(~vga_on_off)		
		hsync<=1'b0		;
	else	if	(cnt_hsync<=10'd95 )
		hsync<=1'b1		;
	else
		hsync<=1'b0		;
	
always@(posedge clk_vga or negedge rst_n_sys	)
	if(~rst_n_sys)
		vsync<=1'b0		;
	else 	if(~vga_on_off)
		vsync<=1'b0		;
	else	if	(cnt_hsync<=10'd783 && cnt_vsync <=10'd1 )
		vsync<=1'b1		;
	else
		vsync<=1'b0		;
		
always@(posedge clk_vga or negedge rst_n_sys	)
	if(~rst_n_sys)
		rgb<=8'H0		;
	else 	if(~vga_on_off)
		rgb<=8'H0		;
	else if(rgb_vaild==1'b1)
		rgb<=pix_data	;
	else
		rgb<=8'Hff	;
endmodule

 

vga_pic模块：

module	vga_pic(
	input	wire	clk_vga				,
	input	wire	rst_n_sys			,
	input	wire	[9:0]pix_x			,
	input	wire	[9:0]pix_y			,
	input	wire	clk_sys				,
	input	wire	[7:0]po_data		,
	input	wire	po_flag				,
	input	wire	vga_on_off			,
	input	wire	[11:0]ram_addr		,
	
	output	reg	[7:0]pix_data	

);

reg	[11:0]rd_addr			;
wire	[7:0]q_pic				;
parameter	lift	=10'd270	,
				right	=10'd319	,
				top	=10'd190	,
				bottom=10'd239	;

parameter	addr_max=2_499	;
				
parameter	a=8'd0		,
				b=8'd28		,
				c=8'd56		,
				aa=8'd84		,
				bb=8'd112	,
				cc=8'd140	,
				aaa=8'd168	,
				bbb=8'd196	,
				ccc=8'd224	;

always@(posedge clk_vga or negedge rst_n_sys)
	if (~rst_n_sys)
		rd_addr<=12'h0				;
	else 	if(~vga_on_off)		
		rd_addr<=12'h0				;
	else	if(rd_addr==addr_max)
		rd_addr<=12'h0				;
	else	if(pix_x<=10'd317 && pix_x>=10'd268 && pix_y>=10'd188 && pix_y<=10'd237 )
		rd_addr<=rd_addr+1'b1	;
	else	
		rd_addr<=rd_addr			;
	
always@(posedge clk_vga or negedge rst_n_sys)
	if(~rst_n_sys)
		pix_data<=8'hff		;
	else 	if(~vga_on_off)		
		pix_data<=8'hff		;			
	else if (pix_y==10'h3ff || pix_x==10'h3ff)
		pix_data<=8'hff		;
	else	if(pix_x<=10'd319 && pix_x>=10'd270 && pix_y>=10'd190 && pix_y<=10'd239)
		pix_data<=q_pic		;
	else if (pix_x<=10'd63)
		pix_data<=a				;
	else if (pix_x<=10'd127)
		pix_data<=b				;
	else if (pix_x<=10'd191)
		pix_data<=c				;			
	else if (pix_x<=10'd255)
		pix_data<=aa			;	
	else if (pix_x<=10'd319)
		pix_data<=bb			;
	else if (pix_x<=10'd447)
		pix_data<=cc			;
	else if (pix_x<=10'd511)
		pix_data<=aaa			;
	else if (pix_x<=10'd511)
		pix_data<=bbb			;
	else if (pix_x<=10'd639)
		pix_data<=ccc			;
	else
		pix_data<=8'hff	;

vga_ram	vga_ram_inst (
	.data 		( po_data 	),
	.rdaddress 	( rd_addr 	),
	.rdclock 	( clk_vga 	),
	.wraddress 	( ram_addr 	),
	.wrclock 	( clk_sys 	),
	.wren 		( po_flag 	),
	.q 			( q_pic 		)
	);

endmodule