FPGA编程入门

一在线Verilog编程网站学习

https://hdlbits.01xz.net/wiki/Main_Page HDLBits — Verilog Practice

二Logisim设计全加器

1全加器

1寻找并添加以下器件。

2按照以下方式连线。

3点击手指图案开始测试。

2四位全加器

1选择途中最右边的图案对一位全加器封装然后新建一个项目。

2放4个四位全加器。

3按照下图方式进行连线。

三Quartus设计全加器

1一位全加器

1原理图实现

2编译然后选择rtl viewer，创建vwf文件，选择Edit->Insert->Insert Node or Bus，添加Node or Bus，编辑输入Clk，产生时钟信号，鼠标选择D，Q信号Q_n,，进行编辑。

3veirilog编程实现

module FullAdder_gate_level (

  input A, B, Cin,

  output Sum, Cout

);

  

  wire X1, X2, X3, X4;

  // XOR gates

  assign X1 = A ^ B;

  assign X2 = X1 ^ Cin;

  // AND gates

  assign X3 = A & B;

  assign X4 = X1 & Cin;

  // OR gates

  assign Sum = X2;

  assign Cout = X3 | X4;

  

endmodule

2四位全加器

门级描述方式

代码

module FourBitAdder_gate_level (

  input [3:0] A, B, Cin,

  output [3:0] Sum, Cout

);

  

  wire C1, C2, C3;

  wire S1, S2, S3;

  FullAdder_gate_level f1 (.A(A[0]), .B(B[0]), .Cin(Cin), .Sum(S1), .Cout(C1));

  FullAdder_gate_level f2 (.A(A[1]), .B(B[1]), .Cin(C1), .Sum(S2), .Cout(C2));

  FullAdder_gate_level f3 (.A(A[2]), .B(B[2]), .Cin(C2), .Sum(S3), .Cout(C3));

  FullAdder_gate_level f4 (.A(A[3]), .B(B[3]), .Cin(C3), .Sum(Sum[3]), .Cout(Cout));

  

endmodule

  

module FullAdder_gate_level (

  input A, B, Cin,

  output Sum, Cout

);

  

  wire X1, X2, X3, X4;

  // XOR gates

  assign X1 = A ^ B;

  assign X2 = X1 ^ Cin;

  // AND gates

  assign X3 = A & B;

  assign X4 = X1 & Cin;

  // OR gates

  assign Sum = X2;

  assign Cout = X3 | X4;

  

endmodule

行为级描述方式

module FullAdder_functional_level (

  input A, B, Cin,

  output Sum, Cout

);

  

  // Full Adder logic

  assign {Cout, Sum} = A + B + Cin;

  

endmodule

  

module FourBitAdder_functional_level (

  input [3:0] A, B, Cin,

  output [3:0] Sum,

  output Cout

);

  

  wire c1, c2, c3;

  FullAdder_functional_level fa1(A[0], B[0], Cin, Sum[0], c1);

  FullAdder_functional_level fa2(A[1], B[1], c1, Sum[1], c2);

  FullAdder_functional_level fa3(A[2], B[2], c2, Sum[2], c3);

  FullAdder_functional_level fa4(A[3], B[3], c3, Sum[3], Cout);

  

endmodule

3RTL电路图