HDLBits刷题之2.1.2----Verilog Language----Basics----Four Wire

2.Four Wire

Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:  a -> w， b -> x， b -> y， c -> z.

题目意思是建立一个拥有3输入和4输出的模块，像上面这个图一样连接起来。代码如下所示：

module top_module( 
    input a,b,c,
    output w,x,y,z );

	assign w = a;
	assign x = b;
	assign y = b;
	assign z = c;

endmodule