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DMA IP核学习笔记
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DMA:外部设备不通过CPU直接与系统内存交互
Xilinx 官方给出的DMA ip核功能介绍:The AXI Direct Memory Access (AXI DMA) IP provides high-bandwidth direct memory
access between the AXI4 memory mapped and AXI4-Stream IP interfaces.
AXI DMA Block Diagram:
应用:The AXI DMA provides high-speed data movement between system memory and an AXI4-Stream-based target IP such as AXI Ethernet.
Vivado AXI DMA IP 核图例:
接口描述:
寄存器地址分配:
低位字节排放在内存的低地址端,高位字节排放在内存的高地址端。
Scatter Mode
Simple Mode
寄存器访问模式类别:
- RO = Read Only. Writing has no effect
- R/W = Read and Write Accessible
- R/WC = Read / Write to Clear
Memory Map to Stream Register Detail
地址00h, MM2S_DMACR 每 bit 的功能描述:
地址04h, MM2S_DMASR 每 bit 的功能描述:
地址08h, MM2S_CURDESC 每 bit 的功能描述:
地址10h, MM2S_TAILDESC 每 bit 的功能描述:
地址18h, MM2S_SA 每 bit 的功能描述:
地址28h, MM2S_LENGTH 每 bit 的功能描述:
Stream to Memory Map Register Detail
地址30h, S2MM_DMACR 每 bit 的功能描述:
地址34h, S2MM_DMASR 每 bit 的功能描述:
地址38h, S2MM_CURDESC 每 bit 的功能描述:
地址40h, S2MM_TAILDESC 每 bit 的功能描述:
地址48h, S2MM_DA 每 bit 的功能描述:
地址58h, S2MM_LENGTH 每 bit 的功能描述:
AXI DMA IP 核设计应用
该设计中涉及四种时钟输入:
- MM2S 交互:m_axi_mm2s_aclk
- S2MM 交互:m_axi_s2mm_aclk
- AXI-Lite 4 控制:s_axi_lite_aclk
- (如果是scatter模式)Scatter gather 交互:m_axi_sg_clk
**asynchronous mode 下可分别挂载不同时钟源,synchronous mode 下用同一时钟源。注意 asynchronous mode 下 s_axi_lite_aclk 小于等于 m_axi_sg_aclk,m_axi_sg_aclk 小于等于 m_axi_mm2s_aclk/m_axi_s2mm_aclk。 **
复位信号:The axi_resetn signal needs to be asserted a minimum of eight of the slowest clock cycles and needs to be synchronized to s_axi_lite_aclk.