4位7段共阴数码管动态显示的verilog代码

最新推荐文章于 2024-04-22 21:32:34 发布

rbin_yao

最新推荐文章于 2024-04-22 21:32:34 发布

阅读量1w

点赞数 13

分类专栏： verilog

本文链接：https://blog.csdn.net/rbin_yao/article/details/106909478

版权

verilog 专栏收录该内容

2 篇文章 1 订阅

订阅专栏

4位7段共阴数码管动态显示的verilog代码

sn_data为输入的显示数值
clk接100MHz时钟
s为数码管位选信号，高电平有效
seg为7段共阴极数码管输出

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/06/22 15:45:38
// Design Name: 
// Module Name: bcd_2_7seg
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module bcd_2_7seg(
        input wire [3:0] s1_data,
        input wire [3:0] s2_data,
        input wire [3:0] s3_data,
        input wire [3:0] s4_data,
        input wire clk,
        output reg [6:0] seg,
        output reg [3:0] s
        );
    
    reg [3:0] data;
    reg [18:0] times;
    
    initial times = 0;
    initial s = 4'b0001;
    
    always @ (posedge clk)
        begin
        times <= times + 19'b1;
        case (times)
            19'd000000: begin s <= 4'b0001; data <= s1_data; end
            19'd100000: begin s <= 4'b0010; data <= s2_data; end
            19'd200000: begin s <= 4'b0100; data <= s3_data; end
            19'd300000: begin s <= 4'b1000; data <= s4_data; end
        endcase
        if(times == 400000)
            times <= 19'b0;
        end
    
    always @ (posedge clk)
    begin
        case(data)
            4'b0000: seg = ~7'b1000000;    //0
            4'b0001: seg = ~7'b1111001;    //1
            4'b0010: seg = ~7'b0100100;    //2
            4'b0011: seg = ~7'b0110000;    //3
            4'b0100: seg = ~7'b0011001;    //4
            4'b0101: seg = ~7'b0010010;    //5
            4'b0110: seg = ~7'b0000010;    //6
            4'b0111: seg = ~7'b1111000;    //7
            4'b1000: seg = ~7'b0000000;    //8
            4'b1001: seg = ~7'b0010000;    //9
            4'b1010: seg = ~7'b0001000;    //A
            4'b1011: seg = ~7'b0000011;    //b
            4'b1100: seg = ~7'b1000110;    //C
            4'b1101: seg = ~7'b0100001;    //d
            4'b1110: seg = ~7'b0000110;    //E
            4'b1111: seg = ~7'b0001110;    //F
        endcase
    end
endmodule