引言
前面,我们介绍过对裸机程序进行RTL仿真,那些裸机程序规模比较小,只有几KB大小。
另外,我们也已经实现了针对O_board的SoC进行了RTL仿真(http://blog.csdn.net/rill_zhen/article/details/21190757),本小节,我们将实现在ML501平台上对linux进行RTL仿真。
1,DDR2仿真模型的修改
针对ML501的ORPSoC工程中,默认配置的DDR2的仿真模型与实际板子上使用的DDR2 SDRAM的参数不一致,我们要进行修改。
a,实际内存参数
要想对DDR2 SDRAM的仿真模型进行修改,我们首先要弄明白几个概念。
RANK,BANK,row,,column。这几个都是逻辑上的概念。
此外还有channel,module,chip,device等物理上的概念。
对于ML501使用的DDR2 SDRAM来说,其具体参数如下所示:
通过查看内存条,我们可以看到如下内容:MT4HTF3264HY-667F1 1RX16 256MB PC-5300S,
其中3263是指内存条的organization:32Megx64,x64表示整个内存条的数据线(DQ)宽度是64bit。
667表示内存条的speed grade。PC-5300也是speed grade。
1RX16表示内存条上面的4个device,每个数据宽度是16,16X4正好是64bit。
256MB,毫无疑问,表示内存条的容量是256M bytes。
通过内存条上面的标示,我们就可以获得很多信息,此外,通过查看其数据手册,我们会得到更详细的参数:
RANK:是single rank。
BANK:BA是2bit,说明bank数量是4,每个bank的大小是256MB/4=64MB。
row:宽度是[12:0],一共13bit。
column:宽度是[9:0],一共10bit。
b,仿真模型参数
确定了我们实际使用的内存条的参数之后,我们就可以修改仿真模型的具体参数了。
需要注意的是ddr2_model.v只是一个timing model,具体的storage,需要我们自己根据实际情况来定。
这里需要修改的是MEM_BITS,由于ddr2_model.v是一个device的仿真模型,每个device中包含4个四分之一的bank,共64MB,所以对于如下定义:
// Memory Storage
`ifdef MAX_MEM
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MAX_SIZE-1];
`else// [8 * 16 -1:0] [0:(1<<22) -1]==>26bit==>64MB
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MEM_SIZE-1];
reg [`MAX_BITS-1:0] address [0:`MEM_SIZE-1];
reg [MEM_BITS:0] memory_index;
reg [MEM_BITS:0] memory_used;
`endif
我们需要定义MEM_BITS为22,如下所示:
完整的参数,如下所示:
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// Parameters current with 512Mb datasheet rev N
// Timing parameters based on Speed Grade
// SYMBOL UNITS DESCRIPTION
`define sg37E
`define x16
//`define MAX_MEM
`ifdef sg37E
parameter TCK_MIN = 3750; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
parameter TQHS = 400; // tQHS ps