Xilinx_FPGA_SOC ERROR1 解决

最新推荐文章于 2024-04-05 16:22:07 发布

huamingshen

最新推荐文章于 2024-04-05 16:22:07 发布

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ERROR:

[NgdBuild 604] logical block 'system_i/chipscope_axi_monitor_0/chipscope_axi_monitor_0/U_ILA' with type 'chipscope_axi_monitor_0' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'chipscope_axi_monitor_0' is not supported in target 'zynq'.

解决方案：

1. Removed directory <PROJECT_NAME>.src/sources_1/edk/<EMBEDDED_NAME>/implementation
2. Removed directory <PROJECT_NAME>.src/sources_1/edk/<EMBEDDED_NAME>/synthesis
3. Created new synthesis and implementation runs.
4. Set the new runs as "active".
5. Removed old runs.
6. Opened XPS by double-clicking in the embedded design under the sources tab.
7. Closed XPS without doing anything.
8. Selected the new synthesis run and clicked on "Reset Selected Runs".
9. Selected the new implementation run and clicked on "Launch Selected Runs".