【xilinx】关于textbench的资料

感谢旁边的巴基斯坦男给我的资料...

Thanks a lot！

Actually test bench code uses the main module as an instant and assigns some values to the input to get some results at the output. That's all... The coding is same Verilog with little difference.
This video gives a good start. https://www.youtube.com/watch?v=pkJAWpkaiHg （请原谅这个英语有点儿重口味）

More about writing test benches: http://www.asic-world.com/verilog/art_testbench_writing.html

More about Xilinx ISim Simulator:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/ug682.pdf

前面附上问题以及解决方法：

Q1: 仿真时间太短，只有1000ns怎么办！

此时可以点击1.00us左边的延时工具，这时就可以一直仿真。

好啦 剩下的为自己总结的：

example1：这个例子是第一个视频里面的，视频里面有教怎么使用仿真

module threeinputOrGate(
    input i1,
    input i2,
    input i3,
    output gateOutput
    );
	 
	 or(gateOutput,i1,i2,i3);


endmodule

testbench

	initial begin
		// Initialize Inputs
		i1 = 0;
		i2 = 0;
		i3 = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		
		#50 i1=1;
		#50 i2=0;
		#60 i3=1;

	end

仿真结果

example2：

module add(
	clk,
	reset,
	a_in,
	b_in,
	c_out
    );
	
	input clk,reset;
	input [7:0]a_in,b_in;
	output reg [8:0]c_out;
	
	always@(posedge clk or negedge reset)
	begin
		if(!reset)
		begin
			c_out <= 9'd0;
		end
		
		else
		begin
			c_out <= a_in + b_in;
		end
	end



endmodule

testbench

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		#100 reset = 1;
		a_in = 0;
		b_in = 0;

        
		// Add stimulus here

	end
	
	
	
	always
	 #10 clk = ~clk;
	
	initial
	begin
		a_in = 1;
		b_in = 3;
		#200 a_in = 2;
		b_in = 0;
		#200 a_in = 3;
		b_in = 3;
	end
	
	initial begin
		$display("\t\ttime,\tclk,\treset,\ta_in,\tb_in,\tc_out");
		$monitor("%d,\t%d,\t%d,%d,\t%d,\t%d",$time,c_out,a_in,b_in,clk,reset);
	end

仿真结果：

example3：

module shift_reg (
	clock, 
	reset, 
	load, 
	sel, 
	data, 
	shiftreg
	);
	
	input clock;
	input reset;
	input load;
	input [1:0] sel;
	input [4:0] data;
	
	output reg [4:0] shiftreg;
	
	always @ (posedge clock)
	begin
		if (reset)
		begin
			shiftreg = 0;
		end

		else if (load)
		begin
			shiftreg = data;
		end

		else
		begin
			case (sel)
				2'b00 : shiftreg = shiftreg;
				2'b01 : shiftreg = shiftreg << 1;
				2'b10 : shiftreg = shiftreg >> 1;
				default : shiftreg = shiftreg;
			endcase
		end
	end
	
	
endmodule

testbench

	initial begin
		// Initialize Inputs
		clock = 0;
		forever #50 clock = ~clock;
	end
	
	initial begin
		reset = 1;
		data = 5'b00000;
		load = 0;
		sel = 2'b00;
		
	#200
	   reset = 0;
	   load = 1;
		
	#200
	   data = 5'b00001;
		
	#100
		sel = 2'b01;
		load = 0;
		
	#200
		sel = 2'b10;
		
	#1000 $stop;
	end
	
	 initial begin// this process block pipes the ASCII results to theterminal or text editor
	 
	 $timeformat(-9,1,"ns",12);
	 $display(" Time Clk Rst Ld SftRg Data Sel");
	 $monitor("%t %b %b %b %b %b %b", $realtime,clock, reset, load, shiftreg, data, sel);
	 
	 end

仿真结果

注意$monitor $time $realtime 是关系到底下绿色格子的显示问题的

example4：

计数器的仿真：（Verilog counter ISE）

module counter(
	clk,
	reset,
	count
    );
	 
	input clk;
	input reset;
	output reg [3:0]count;
	
	always@(posedge clk or negedge reset)
	begin
		if(!reset)
		begin
			count <= 1'd0;
		end
		
		else
		begin
			count <= count + 1'd1;
		end
	end


endmodule

testbench:

module conuter_test;

	// Inputs
	reg clk;
	reg reset;

	// Outputs
	wire [3:0] count;

	// Instantiate the Unit Under Test (UUT)
	counter uut (
		.clk(clk), 
		.reset(reset), 
		.count(count)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		# 50 reset = 1;

		// Wait 100 ns for global reset to finish
        
		// Add stimulus here

	end
	
	always
		#5 clk = ! clk;
    
endmodule

仿真结果：