之前看到别的文章里面的全加器验证,现自己参照复习一下,并修改了一些错误,调试过后的代码如下:
参照链接:
32bit全加器验证
一、32bit全加器RTL代码:
module fulladder32(
input wire [31:0] a_in ,
input wire [31:0] b_in ,
input wire [0:0] c_in ,
output reg [31:0] sum ,
output reg [0:0] c_out
);
assign {c_out,sum} = a_in + b_in + c_in;
endmodule
二、全加器Testbench:
`timescale 1ns/1ps
module fulladder32_tb();
//fulladder
reg [31:0] a_in ;
reg [31:0] b_in ;
reg [0:0] c_in ;
wire [31:0] sum ;
wire [0:0] c_out;
//internal signals
reg [32:0] data_in [3] = {'b0,'b0,'b0}; //33位,最高为为进位
reg [32:0] dut_sum [$]; //队列存放dut的结果
reg [32:0] ref_sum [$]; //队列存放ref的结果
reg data_gen_finish; //标记信号1
event dut_ready; //每一次数据产生完成后,输入到dut
event all_data_generate_finish; //所有数据产生完成后,开始数据比较
reg [32:0] dut_result; //用于结果对比
reg [32:0] gld_result; //用于结果对比
int Error_cnt;
int seed;
int sti_num;
//fetch seed from script
initial begin
if(!$value$plusargs("seed=%d",seed))begin
seed = 99;
$display("seed = %d",seed);end
else
$display("%0t:seed = %d",$time,seed);
if(!$value$plusargs("sti_num=%d",sti_num))begin
sti_num = 3;
$display("sti_num = %d",sti_num);end
else
$display("%0t:sti_num = %d",$time,sti_num);
end
//generate random data
initial begin
data_gen_finish = 0;
repeat(sti_num)begin
data_gen_finish = 0;
#5; //!!!,necessary,used for data alignment
data_in[0][31:0] =$random(seed);
data_in[1][31:0] =$random(seed);
data_in[2] = 1'b0;
$display("%t:data:%0h,%h,%h",$time,data_in[0],data_in[1],data_in[2]);
data_gen_finish = 1;
#20;//used for 'data_gen_finish' detection
// $display("data_gen_finish = %b",data_gen_finish);
end
-> all_data_generate_finish; //all random data are transferred in dut and golden model
end
//random data to dut; dut result collection
initial begin
repeat(sti_num)begin
//$display("%t:data_gen_finish",$time);
@(posedge data_gen_finish)begin
a_in = data_in[0];
b_in = data_in[1];
c_in = data_in[2];
$display("%t:a:%0h,%h,%h",$time,a_in,b_in,c_in);
-> dut_ready;end
end
end
initial begin
repeat(sti_num)begin
@dut_ready begin
dut_sum.push_back({c_out,sum});
$display("c_out_sum=%h",{c_out,sum});
end
end
end
//random data to golden model
initial begin
repeat(sti_num)begin
@(posedge data_gen_finish)begin
gld_sum.push_back(data_in.sum);
$display("gld_sum=%h",data_in.sum);
end
end
end
// data compare
initial begin
Error_cnt = 0;
@all_data_generate_finish
repeat(sti_num)begin
dut_result = dut_sum.pop_front();
gld_result = gld_sum.pop_front();
if(dut_result != gld_result)begin
$display("@%0t:Error:gld_result != dut_result---gld_result =%0h;dut_result = %0h ",$time,gld_result,dut_result);
Error_cnt++;
end
end
if(Error_cnt == 0)begin
$display("--------------------------------");
$display("--------------------------------");
$display("--------------PASS--------------");
$display("--------------------------------");
$display("--------------------------------");
end
end
fulladder32 fulladder32_u0(
.a_in(a_in),
.b_in(b_in),
.c_in(c_in),
.sum (sum) ,
.c_out(c_out)
);
endmodule
三、Makefile:
comp_file = ./fulladder32_tb.v\
./fulladder32.v
seed = $(shell date +%s)
sti_num = 100
all:comp sim
comp:
vcs -sverilog +v2k -debug_all $(comp_file) -l comp.log
sim:
./simv -l sim_log_$(seed) +plusarg_save +seed=$(seed) +sti_num=$(sti_num)
dump:
dve -vpd vcdplus.vpd &
clean:
rm -rf *.log sim* csrc ucli.key *.vpd DVEfiles
Makefile里面各项含义参照:https://blog.csdn.net/weixin_46022434/article/details/105075703
四、结果:
运行:make sti_num=1000
结果: