【nios开发】- 问题3：使用quartus 23.3编译nios II出现13223 verilog HDL or VHDL error：cannot open verilog file

错误

可能是quartus prime pro23.3版本太新，而nios ii过于老旧，在编译的过程中就会报错

13223 verilog HDL or VHDL error：cannot open verilog file

项目生成过程

参考链接：

Nios初体验之——Hello world!-CSDN博客

qsys设计如下

其中nios系统已经提示不要使用

Warning: nios2_gen2_0: Nios II cores are not recommended for new projects and are subject to removal in a future release. Nios V cores are the recommended replacement as applicable.
 

问题来源

ID:13223 Verilog HDL or VHDL error: <text>

CAUSE: Quartus Prime Integrated Synthesis generated the specified error for a Verilog Design File (.v) or VHDL Design File (.vhd).

ACTION: Edit the file to correct the error. A future version of the Quartus Prime software will provide more detailed information about this error.

这里也没有提到怎么解决，我需要换个版本试试，有结果再更新。

参考：

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/evrfx2_generic_error.htm