Verilog :Exams/ece241 2013 q4/Design a Moore FSM/水库

传送门：

Exams/ece241 2013 q4 - HDLBits (01xz.net)https://hdlbits.01xz.net/wiki/Exams/ece241_2013_q4

代码：

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
	parameter S0=0,S1=1,S2=2,S3=3;
	reg [1:0] state,next_state;
    always @(*) begin
        if (s[1]&s[2]&s[3])
            next_state = S3;        
        else if (s[1]&s[2]&~s[3])
            next_state = S2;     
        else if (s[1]&~s[2]&~s[3])   
            next_state = S1;    
        else if (~s[1]&~s[2]&~s[3])
            next_state = S0;
    end
	always @(*) begin
        if(state==S0)begin
            fr1 =1;
            fr2 =1;
            fr3 =1;
        end
        else if(state==S1)begin
            fr1 =1;
            fr2 =1;
            fr3 =0;
        end
        else if(state==S2)begin
            fr1 =1;
            fr2 =0;             
            fr3 =0;
        end
        else if(state==S3)begin
            fr1 =0;
            fr2 =0;             
            fr3 =0;
        end
    end
	always @(posedge clk) begin
        if(reset)begin
            state<=S0; 
        	dfr <= 1;
        end
        else begin 
            dfr <= (state > next_state)?1:((state == next_state)?dfr:0);   
            state<=next_state;
        end
    end

endmodule