【xilinx】Vivado ： 解决 I/O 时钟布局器错误：Versal 示例

示例详细信息：

设备： XCVM1802 Versal Prime
问题：尽管使用 CCIO 引脚作为时钟端口，但该工具仍返回 I/O 时钟布局器错误

错误：

<span style="background-color:#f3f3f3"><span style="color:#333333"><code>ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets <output net of input buffer>] >
 
    <Differential input buffer name> (IBUFDS.O) is locked to IOB_X14Y9
    <Clock Buffer BUFGCE> (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X2Y23
 
    The above error could possibly be related to other connected instances. Following is a list of
    all the related clock rules and their respective instances.
 
    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    <Clock Buffer BUFGCE> (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X2Y23
 
Resolution: A dedicated routing path between the two can be used if: (a) The global clock-capable IO (GCIO) is placed on a GCIO capable site (b) The BUFG is placed in the same bank of the device as the GCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays.
ERROR: [Place 30-1161] Could not place all instances for rule!
    Clock Rule: rule_bufg_ctrl_in_shadow_regions_driven_by_one_fabric
    Rule Description: Only one connection is available for BUFGCE/BUFGCTRL driven by a non IO/Clock element in shadow clock regions.
 
    <Load> (FDRE.Q) cannot be placed
    <Another Clock buffer> (BUFGCTRL.I1) is provisionally placed by clockplacer on BUFGCTRL_X11Y7 Please ensure there are no physical constraint that prevent a legal placement.
 
ERROR: [Place 30-1161] Could not place all instances for rule!
    Clock Rule: rule_bufg_ctrl_in_shadow_regions_driven_by_one_fabric
    Rule Description: Only one connection is available for BUFGCE/BUFGCTRL driven by a non IO/Clock element in shadow clock regions.
 
    <Load> (FDRE.Q) cannot be placed
    <Another Clock Buffer> (BUFGCTRL.I1) is provisionally placed by clockplacer on BUFGCTRL_X11Y6 Please ensure there are no physical constraint that prevent a legal placement.</code></span></span>

当我们生成网络的原理图并将其扩展到该网络的源和负载时，我们得到以下原理图。

这里，端口被分配给来自 HDIO 组的 CCIO 引脚，该引脚位于设备左上角的时钟区域，即 L35，而 BUFGCE 则由 I/O 时钟布局器放置在设备的底行时钟区域。

将此行为与表中的规则 1 关联，很明显该工具应该将 BUFG 放置在与端口（即 X0Y4）相同的时钟区域。

使用以下命令列出时钟区域X0Y4中的所有BUFG，我们可以看到有一些可用的BUFG。

show_objects [get_sites -filter {CLOCK_REGION == X0Y4 } BUFGCE*]

因此决定的约束是 BUFG 上的 CLOCK_REGION 到 X0Y4

set_property CLOCK_REGION X0Y4 [get_cells <BUFG>]  

在随后的约束运行中，该工具在放置过程中没有出错，并且发现所有的 BUFG 都被放置到同一个时钟区域，因此遵循规则 1。

注意：黄色标记的站点和蓝色标记的站点是 X0Y4 时钟区域中的 BUFGCE 站点。

查看此设计中此端口和 BUFG 的完整行为，它看起来像是一个错误，已在 Vivado 的后续版本中修复。（苏拉杰·乔索）