1.实验目的:
实验一.Verilog HDL测试模块仿真
实验二.时序逻辑的测试模块``
代码一:
module decoder3x8(din, en, dout, ex);
input [2:0] din;
input en;
output [7:0] dout;
output ex;
reg [7:0] dout;
reg ex;
always @(din or en)
if(en)
begin
dout=8’b1111_1111;
ex=1’b1;
end
else
begin
case(din)
3’b000: begin
dout=8’b1111_1110;
ex=1’b0;
end
3’b001: begin
dout=8’b1111_1101;
ex=1’b0;
end
3’b010: begin
dout=8’b1111_1011;
ex=1’b0;
end
3’b011: begin
dout=8’b1111_0111;
ex=1’b0;
end
3’b100: begin
dout=8’b1110_1111;
ex=1’b0;
end
3’b101: begin
dout=8’b1101_1111;
ex=1’b0;
end
3’b110: begin
dout=8’b1011_1111;
ex=1’b0;
end
3’b111: begin
dout=8’b0111_