- latch有什么坏处?如何避免latch?
// 1. latch
always @ (enable or d)
if (enable)
q = d;
- 怎么用Verilog描写同步和异步复位?并说说它们的优缺点?
//asynchronous reset
always @(posedge clk or negedge rst_n)
if(!rst_n)
a <= 0;
else
...
//synchronous reset
always @(posedge clk)
if(!rst_n)
a <= 0;
else
...