verilog 1bit跨时钟同步器

快时钟到慢时钟有周期要求，不能太密集，至少间隔一个慢周期

//Synchronous
module tongbu(
    input           clka,
    input           clkb,
    input           rst_n,
    input           pulse_ina,
    output          pulse_outb,
    output          signal_outb
);

//-------------------------------------------------------
reg             signal_a;
reg     [1:0]   signal_b_r;

//-------------------------------------------------------
always @(negedge rst_n or posedge clka)begin
if(!rst_n)begin
    signal_a<=0;
end
else if(pulse_ina)
    signal_a<=1;
else if(signal_b_r[0]==1)
    signal_a<=0;
else
    signal_a<=signal_a;
end


always @(negedge rst_n or posedge clkb)begin
if(!rst_n)begin
    signal_b_r<=0;
end
else 
    signal_b_r<={signal_b_r[0],signal_a};
end
assign pulse_outb=~signal_b_r[1] & signal_b_r[0];
assign signal_outb=signal_b_r[1];
endmodule

tb：

`timescale 1ns/1ns
module tongbu_tb();
reg clka,clkb,a,rst;
wire b,signal_outb;

tongbu tongbu1(.clka(clka),.clkb(clkb),.pulse_ina(a),.pulse_outb(b),.rst_n(rst),.signal_outb(signal_outb));

initial begin
clka=1;
clkb=1;
a=0;
rst=1;
#2 rst=0;
#1 rst=1;
#22 a=1;
#10 a=0;


//#55 a=1;
//#60 a=0;
#300 $finish;
end
always #5 clka=~clka;
always #10 clkb=~clkb;

endmodule

结果：