MCP3561驱动程序

 ADC mcp3561芯片msp30的 驱动程序。

.h:

#ifndef __MCP3561_H__
#define __MCP3561_H__
#ifdef __cplusplus
extern "C"
{
#endif
//register map

#define MCP3561_NUM_CONFIG_REGS  ((uint8_t) 0x05) 
  
#define REG_ADDR_CONFIG0  ((uint8_t) 0x01)
/* Register 0x01 (CONFIG0) definition
 *  * ---------------------------------------------------------------------------------
 * ---------------------------------------------------------------------------------
 * |  Bit 7  |  Bit 6  |  Bit 5  |  Bit 4  |  Bit 3  |  Bit 2  |  Bit 1  |  Bit 0  |
 * ---------------------------------------------------------------------------------
  * |   CONFIG0[7:0]  |   CLK_SEL[1:0]    |  CS_SEL[1:0]      |  ADC_MODE[1:0]    |
 * ---------------------------------------------------------------------------------
 */
#define CONFIG0_DEFAULT       ((uint8_t) 0xC0)
#define CONFIG0_CONFIG0_MASK  ((uint8_t) 0xC0)    //bit7:6 =11:Full shutdown mode;= 00: 

#define CONFIG0_CLK_INTERNAL ((uint8_t) 0x30)    //bit5:4 =11:Internal clock&AMCLK on output pin ;= 10: Internal clock
#define CONFIG0_CLK_EXTERNAL ((uint8_t) 0x00)    //bit5:4 =01:ernal digital clock  ;= 00:External digital clock (default)

#define CONFIG0_CS_SEL        ((uint8_t) 0x00)    //bit3:2 = 11：15 μA is applied to the ADC inputs
                                                  //       = 10: 3.7 μA is applied to the ADC inputs
                                                  //       = 01: 0.9 μA is applied to the ADC inputs
                                                  //       =00: No current source is applied to the ADC inputs (default)
#define CONFIG0_ADC_CONVERSION_MODE       ((uint8_t) 0x03)  //bit1:0 = 11:ADC Conversion mode
#define CONFIG0_ADC_STANDBY_MODE          ((uint8_t) 0x02)  //       = 10:ADC Standby mode
#define CONFIG0_ADC_SHUTDOWN_MODE         ((uint8_t) 0x01)  //       = 01:ADC Shutdown mode



#define REG_ADDR_CONFIG1  ((uint8_t) 0x02)
/* Register 0x02 (CONFIG1) definition
 *  * ---------------------------------------------------------------------------------
 * ---------------------------------------------------------------------------------
 * |  Bit 7  |  Bit 6  |  Bit 5  |  Bit 4  |  Bit 3  |  Bit 2  |  Bit 1  |  Bit 0  |
 * ---------------------------------------------------------------------------------
 * |   PRE[1:0]  |                OSR[3:0]                   |  RESERVED[1:0]    |
 * ---------------------------------------------------------------------------------
 */                                              
#define CONFIG1_DEFAULT              ((uint8_t) 0x0C)
#define CONFIG1_PRE_MCLKD8           ((uint8_t) 0xC0) //PRE7:6 =11 :AMCLK = MCLK/8
#define CONFIG1_PRE_MCLKD4           ((uint8_t) 0x80) //PRE7:6 =10 :AMCLK = MCLK/4 
#define CONFIG1_PRE_MCLKD2           ((uint8_t) 0x40) //PRE7:6 =01 :AMCLK = MCLK/2 
#define CONFIG1_PRE_MCLKD1           ((uint8_t) 0x00) //PRE7:6 =00 :AMCLK = MCLK 

#define CONFIG1_OSR_98304            ((uint8_t) 0x3C) //PRE5:2 =1111
#define CONFIG1_OSR_81920            ((uint8_t) 0x38)
#define CONFIG1_OSR_49152            ((uint8_t) 0x34) 
#define CONFIG1_OSR_40960            ((uint8_t) 0x30)
#define CONFIG1_OSR_24576            ((uint8_t) 0x2C) 
#define CONFIG1_OSR_20480            ((uint8_t) 0x28)
#define CONFIG1_OSR_16384            ((uint8_t) 0x24) 
#define CONFIG1_OSR_8192             ((uint8_t) 0x20)
#define CONFIG1_OSR_4096             ((uint8_t) 0x1C) 
#define CONFIG1_OSR_2048             ((uint8_t) 0x18)
#define CONFIG1_OSR_1024             ((uint8_t) 0x14) 
#define CONFIG1_OSR_512              ((uint8_t) 0x10)
#define CONFIG1_OSR_256              ((uint8_t) 0x0C) 
#define CONFIG1_OSR_128              ((uint8_t) 0x08)
#define CONFIG1_OSR_64               ((uint8_t) 0x04) 
#define CONFIG1_OSR_32               ((uint8_t) 0x00)
  
#define REG_ADDR_CONFIG2  ((uint8_t) 0x03)
/* Register 0x03 (CONFIG2) definition
 *  * ---------------------------------------------------------------------------------
 * ---------------------------------------------------------------------------------
 * |  Bit 7  |  Bit 6  |  Bit 5  |  Bit 4  |  Bit 3  |  Bit 2  |  Bit 1  |  Bit 0  |
 * ---------------------------------------------------------------------------------
 * |   BOOST[1:0]     |      GAIN[2:0]              |  AZ_MUX | RESERVED[1:0]    |
 * ---------------------------------------------------------------------------------
 */  
#define CONFIG2_DEFAULT       ((uint8_t) 0x8B)
#define CONFIG2_BOOST_2       ((uint8_t) 0xC0)
#define CONFIG2_BOOST_1       ((uint8_t) 0x80) //default
#define CONFIG2_BOOST_0_66    ((uint8_t) 0x40)
#define CONFIG2_BOOST_0_5     ((uint8_t) 0x00)

#define CONFIG2_GAIN_64      ((uint8_t) 0x38)  
#define CONFIG2_GAIN_32      ((uint8_t) 0x30)
#define CONFIG2_GAIN_16      ((uint8_t) 0x28)  
#define CONFIG2_GAIN_8       ((uint8_t) 0x20)
#define CONFIG2_GAIN_4       ((uint8_t) 0x18)  
#define CONFIG2_GAIN_2       ((uint8_t) 0x10)
#define CONFIG2_GAIN_1       ((uint8_t) 0x08)  
#define CONFIG2_GAIN_1D3     ((uint8_t) 0x00)

#define CONFIG2_AZ_MUX_ENABLE     ((uint8_t) 0x04)
#define CONFIG2_AZ_MUX_DISABLE    ((uint8_t) 0x00) 
#define CONFIG2_RESERVED          ((uint8_t) 0x03) 

  
#define REG_ADDR_CONFIG3  ((uint8_t) 0x04)
/* Register 0x04 (CONFIG3) definition
 *  * ---------------------------------------------------------------------------------
 * ---------------------------------------------------------------------------------
 * |  Bit 7  |  Bit 6  |  Bit 5  |  Bit 4  |  Bit 3  |  Bit 2  |  Bit 1  |  Bit 0  |
 * ---------------------------------------------------------------------------------
 * |  CONV_MODE[1:0]  |  DATA_FORMAT[1:0] |CRC_FORMT|EN_CRCCOM|EN_OFFCAL|EN_GAINCAL|
 * ---------------------------------------------------------------------------------
 */
#define CONFIG3_DEFAULT          ((uint8_t) 0x00)
#define CONFIG3_CONV_CONTINOUS   ((uint8_t) 0xC0)
#define CONFIG3_CONV_ONE_SHOT1    ((uint8_t) 0x80)//ADC_MODE[1:0] to ‘10’ (standby)
#define CONFIG3_CONV_ONE_SHOT2    ((uint8_t) 0x00)// ADC_MODE[1:0] to ‘0x’ (ADC Shutdown)

#define CONFIG3_DATA_FORMAT32_1    ((uint8_t) 0x30)//CHID[3:0] + SGN extension (4 bits) + 24-bit ADC data
#define CONFIG3_DATA_FORMAT32_2    ((uint8_t) 0x20)//SGN extension (8-bit) + 24-bit ADC data
#define CONFIG3_DATA_FORMAT32_3    ((uint8_t) 0x10)//24-bit ADC data + 0x00 (8-bit).
#define CONFIG3_DATA_FORMAT24      ((uint8_t) 0x00)//24-bit ADC data

#define CONFIG3_CRC_FORMAT_32_BIT        ((uint8_t) 0x08)//32-bit wide (CRC-16 followed by 16 zeros)
#define CONFIG3_CRC_FORMAT_16_BIT        ((uint8_t) 0x00)//16-bit wide (CRC-16 only) (default)

#define CONFIG3_CRCCOM_ENABLE         ((uint8_t) 0x04)// CRC on communications enabled
#define CONFIG3_CRCCOM_DISABLE        ((uint8_t) 0x00)//CRC on communications disabled (default)

#define CONFIG3_OFFCAL_ENABLE         ((uint8_t) 0x02)// Enable Digital Offset Calibration
#define CONFIG3_OFFCAL_DISABLE        ((uint8_t) 0x00)//

#define CONFIG3_GAINCAL_ENABLE         ((uint8_t) 0x01)// Enable Digital Gain Calibration
#define CONFIG3_GAINCAL_DISABLE        ((uint8_t) 0x00)//

#define REG_ADDR_IRQ  ((uint8_t) 0x05)
/* Register 0x05 (IRQ) definition
 *  * ---------------------------------------------------------------------------------
 * ---------------------------------------------------------------------------------
 * |  Bit 7  |  Bit 6  |  Bit 5  |  Bit 4  |  Bit 3  |  Bit 2  |  Bit 1  |  Bit 0  |
 * ---------------------------------------------------------------------------------
 * |    — |/DR_STATUS|CRCCFG_ST|/POR_STA |IRQ_MODE[1:0]      |EN_FASCMD| EN_STP  |
 * ---------------------------------------------------------------------------------
 */
#define IRQ_DEFAULT          ((uint8_t) 0x73)
#define MUX_DEFAULT          ((uint8_t) 0x01)
#define SCAN_DEFAULT         ((uint32_t) 0x00)
#define TIME_DEFAULT         ((uint32_t) 0x00)
#define OFFSET_DEFAULT       ((uint32_t) 0x00)
#define GAIN_DEFAULT         ((uint32_t) 0x800000)
#define RESERVED1_DEFAULT    ((uint32_t) 0x900000)
#define RESERVED2_DEFAULT    ((uint8_t) 0x50)
#define LOCK_DEFAULT         ((uint8_t) 0xA5)
#define RESERVED3_DEFAULT    ((uint16_t)0x0C)
#define CRC_DEFAULT          ((uint16_t) 0x00)
//
  
#define _ADCDATA_ 0x00                      //MCP3561 ADCDATA Register Address.        
#define _CONFIG0_ 0x01                      //MCP3561 CONFIG0 Register Address.
#define _CONFIG1_ 0x02                      //MCP3561 CONFIG1 Register Address.
#define _CONFIG2_ 0x03                      //MCP3561 CONFIG2 Register Address.
#define _CONFIG3_ 0x04                      //MCP3561 CONFIF3 Register Address.
#define _IRQ_ 0x05                          //MCP3561 IRQ Register Address.
#define _MUX_ 0x06                          //MCP3561 MUX Register Address.
#define _SCAN_ 0x07                         //MCP3561 SCAN Register Address.
#define _TIMER_ 0x08                        //MCP3561 TIMER Register Address.
#define _OFFSETCAL_ 0x09                    //MCP3561 OFFSETCAL Register Address.
#define _GAINCAL_ 0x0A                      //MCP3561 GAINCAL Register Address.
#define _RESERVED_B_ 0x0B                   //MCP3561 Reserved B Register Address.
#define _RESERVED_C_ 0x0C                   //MCP3561 Reserved C Register Address.
#define _LOCK_ 0x0D                         //MCP3561 LOCK Register Address.
#define _RESERVED_E_ 0x0E                   //MCP3561 Reserved E Register Address.
#define _CRCCFG_ 0x0F                       //MCP3561 CRCCFG Register Address.

#define _WRT_CTRL_ (0b01000010)               //MCP3561 Write-CMD Command-Byte.
#define _RD_CTRL_  (0b01000001)               //MCP3561 Read-CMD Command-Byte.
  

#define Dummy_Byte              0xFF
#define DEVICE_ADDRESS 			0x01

//COMMAND字节组成
#define DEVICE_ADDR_POS 		6
#define COMMAND_ADDR_POS 		2

#define SREAD_COMMAND_MASK 		0x01 //静态读取
#define SREAD_COMMAND 			((DEVICE_ADDRESS<<DEVICE_ADDR_POS) |SREAD_COMMAND_MASK)

#define WRITE_COMMAND_MASK 		0x02 //递增写入
#define WRITE_COMMAND 			((DEVICE_ADDRESS<<DEVICE_ADDR_POS) |WRITE_COMMAND_MASK)

#define IREAD_COMMAND_MASK 		0x03 //递增读取
#define IREAD_COMMAND 			((DEVICE_ADDRESS<<DEVICE_ADDR_POS) |IREAD_COMMAND_MASK)
#define IREAD_CONFIG 			((CONFIG0_ADDR << COMMAND_ADDR_POS) | IREAD_COMMAND)

//STATUS字节组成
#define DR_STATUS_MASK 			0x04
#define DEV_ADDR_MASK			0x30

//ADCDATA寄存器
#define ADCDATA_ADDR 			0x00

//CONFIG0寄存器
#define CONFIG0_ADDR 			0x01
#define CONFIG0_WRITE 			((CONFIG0_ADDR << COMMAND_ADDR_POS) | WRITE_COMMAND)

//CONFIG1寄存器
#define CONFIG1_ADDR 			0x02
#define CONFIG1_WRITE 			((CONFIG1_ADDR << COMMAND_ADDR_POS) | WRITE_COMMAND)

//CONFIG2寄存器
#define CONFIG2_ADDR 			0x03
#define CONFIG2_WRITE 			((CONFIG2_ADDR << COMMAND_ADDR_POS) | WRITE_COMMAND)

//CONFIG3寄存器
#define CONFIG3_ADDR 			0x04
#define CONFIG3_WRITE 			((CONFIG3_ADDR << COMMAND_ADDR_POS) | WRITE_COMMAND)

//IRQ寄存器
#define IRQ_ADDR 			0x05
#define IRQ_WRITE 		        ((IRQ_ADDR << COMMAND_ADDR_POS) | WRITE_COMMAND)

//SCAN寄存器
#define SCAN_ADDR 			0x07
#define SCAN_WRITE 			((SCAN_ADDR << COMMAND_ADDR_POS) | WRITE_COMMAND)

//TIMER寄存器
#define TIMER_ADDR 			0x08
#define TIMER_WRITE 			((TIMER_ADDR << COMMAND_ADDR_POS) | WRITE_COMMAND)

//OFFSETCAL寄存器
#define OFFSETCAL_ADDR 			0x09
#define OFFSETCAL_WRITE 		((OFFSETCAL_ADDR << COMMAND_ADDR_POS) | WRITE_COMMAND)

//快速命令
#define FASTCMD_UNUSE 			((DEVICE_ADDRESS<<DEVICE_ADDR_POS) | (0x00<<COMMAND_ADDR_POS) | 0x00)
#define FASTCMD_ADCSTART 		((DEVICE_ADDRESS<<DEVICE_ADDR_POS) | (0x0A<<COMMAND_ADDR_POS) | 0x00)
#define FASTCMD_STANDBY			((DEVICE_ADDRESS<<DEVICE_ADDR_POS) | (0x0B<<COMMAND_ADDR_POS) | 0x00)
#define FASTCMD_SHUTDOWN 		((DEVICE_ADDRESS<<DEVICE_ADDR_POS) | (0x0C<<COMMAND_ADDR_POS) | 0x00)
#define FASTCMD_FULLSHUTDOWN 	        ((DEVICE_ADDRESS<<DEVICE_ADDR_POS) | (0x0D<<COMMAND_ADDR_POS) | 0x00)
#define FASTCMD_RESET 			((DEVICE_ADDRESS<<DEVICE_ADDR_POS) | (0x0E<<COMMAND_ADDR_POS) | 0x00)

  
 typedef struct
{
	uint8_t config0;
	uint8_t config1;
	uint8_t config2;
	uint8_t config3;
	uint8_t irp;
	uint8_t mux;
	uint8_t scan[3];
	uint8_t timer[3];
	uint8_t offsetcal[3];
	uint8_t gaincal[3];
	uint8_t reserved1[3];
	uint8_t reserved2;
	uint8_t lock;
	uint8_t reserved3[2];
	uint8_t crccfg[2];
}_mcp3561_config;
typedef struct
{
	uint8_t status;
	uint8_t adcdata[4];	//3561返回的adc原始数据
}_mcp3561_data;

extern _mcp3561_config MCP3561_Config;
extern _mcp3561_data MCP3561_Data;
extern  uint8_t mcp3561_config[12];

extern void MCP3561_CS_LOW(void);
extern void MCP3561_CS_HIGH(void);
extern uint8_t MCP3561_SendByte(uint8_t byte);
extern void MCP3561_SendConfig(void);
extern void MCP3561_Write(uint8_t* pBuffer, uint8_t Cmd, uint8_t NumByteToWrite);
extern void MCP3561_Read(uint8_t* pBuffer, uint8_t Cmd, uint8_t NumByteToRead);
extern uint8_t MCP3561_GetStatus(void);
extern void MCP3561_FastCMD(uint8_t Cmd);
extern void MCP3561_StartupRoutinePGAMode(uint8_t adc_pga);
extern uint16_t MCP3561_PGAGainSetting(uint8_t pga_gainsetting);
extern void readRdataRegisterMcp3561();
#ifdef __cplusplus
}
#endif
#endif

.C: 

#include <msp430.h>
#include <stdio.h>
#include <string.h>
#include <ctype.h>
#include <stdint.h>
#include "driverlib.h"
#include "board.h"
#include "bsp_spi_adc.h"
#include "mcp3561.h"


 _mcp3561_config MCP3561_Config;
 _mcp3561_data MCP3561_Data;
uint8_t mcp3561_config[12]=
{				        //从config0开始写
	0x30, 				//config0：0011 0011，内部时钟，ADC关断模式
	0x0C,				//config1：0000 1100，OSR256  转换时间，768个DMCLK周期
	0x8B, 				//config2：1000 1011，增益为1，
	0xF3, 				//config3：1111 0011，连续转换模式，32位数据，使能数字失调校准,使能数字增益校准
	0x73,				//IRQ：IRQ
	0x01,				//mux：
	0xE0,0x11,0x00,		        //SCAN：512个DMCLK间隔，... ... 7 6 5 4 3 2 1 0
	0x00,0x00,0x00,		        //timer：无延时
};//配置0-3

uint8_t readSingleRegister_MCP3561(uint8_t addr)
{
    uint8_t DataRx[4] = {0};
    uint8_t byteLen = 2;
    uint8_t dataPosition = 1;
    
    return DataRx[dataPosition];
}

 void MCP3561_CS_LOW(void)
{
	P5OUT &= ~BIT3;
}

 void MCP3561_CS_HIGH(void)
{
	P5OUT |= BIT3;
}

uint8_t MCP3561_SendByte(uint8_t byte)
{
// 写入数据寄存器
     EUSCI_B_SPI_transmitData(EUSCI_B1_BASE,byte);
     while(EUSCI_B_SPI_isBusy(EUSCI_B1_BASE));
     return UCB1RXBUF;
}



void MCP3561_Write(uint8_t* pBuffer, uint8_t Cmd, uint8_t NumByteToWrite)
{
	MCP3561_CS_LOW();
	MCP3561_SendByte(Cmd);
	while (NumByteToWrite--)
	{
            MCP3561_SendByte(*pBuffer);
            pBuffer++;
	}
	MCP3561_CS_HIGH(); 
}


void MCP3561_Read(uint8_t* pBuffer, uint8_t Cmd, uint8_t NumByteToRead)
{	
	MCP3561_CS_LOW();
	MCP3561_SendByte(Cmd);
	while (NumByteToRead--)
	{
		*pBuffer = MCP3561_SendByte(Dummy_Byte);
		pBuffer++;
	}
	MCP3561_CS_HIGH();
}

void MCP3561_SendConfig(void)
{
    MCP3561_Write((uint8_t*)mcp3561_config,CONFIG0_WRITE,sizeof(mcp3561_config));
}


uint8_t MCP3561_GetStatus(void)
{
	uint8_t status=0;
	
	MCP3561_CS_LOW();

	status=MCP3561_SendByte(FASTCMD_UNUSE);//0100 0000

	MCP3561_CS_HIGH();
	
	return status;
}

void MCP3561_FastCMD(uint8_t Cmd)
{
	MCP3561_CS_LOW();

	MCP3561_SendByte(Cmd);
	
	MCP3561_CS_HIGH();
}

void MCP3561_StartupRoutinePGAMode(uint8_t adc_pga)
{
  uint8_t initRegisterConfig[MCP3561_NUM_CONFIG_REGS];
  initRegisterConfig[REG_ADDR_CONFIG0 -1] = CONFIG0_CLK_EXTERNAL | CONFIG0_ADC_CONVERSION_MODE ;
  initRegisterConfig[REG_ADDR_CONFIG1 -1] = CONFIG1_PRE_MCLKD1 | CONFIG1_OSR_256;
  initRegisterConfig[REG_ADDR_CONFIG2 -1] = CONFIG2_BOOST_1 | CONFIG2_GAIN_16;
  initRegisterConfig[REG_ADDR_CONFIG3 -1] = CONFIG3_CONV_CONTINOUS | CONFIG3_DATA_FORMAT24;
  initRegisterConfig[REG_ADDR_IRQ -1]     = IRQ_DEFAULT;
  MCP3561_Write((uint8_t*)initRegisterConfig,CONFIG0_WRITE, MCP3561_NUM_CONFIG_REGS);
  MCP3561_Read(&MCP3561_Config.config0,IREAD_CONFIG,MCP3561_NUM_CONFIG_REGS);
}


uint16_t MCP3561_PGAGainSetting(uint8_t pga_gainsetting)
{
  uint8_t tmp_pgaGain = 0;
  switch(pga_gainsetting)
  {

  case 1:
    tmp_pgaGain = CONFIG2_GAIN_1;
    break;
  case 2:
    tmp_pgaGain = CONFIG2_GAIN_2;
    break;
  case 4:
    tmp_pgaGain = CONFIG2_GAIN_4;
    break;
  case 8:
    tmp_pgaGain = CONFIG2_GAIN_8;
    break;
  case 16:
    tmp_pgaGain = CONFIG2_GAIN_16;
    break;
  case 32:
    tmp_pgaGain = CONFIG2_GAIN_32;
    break;
  case 64:
    tmp_pgaGain = CONFIG2_GAIN_64;
    break;
  default:
    tmp_pgaGain = CONFIG2_GAIN_1;
    break;
 
  }

}


void readRdataRegisterMcp3561()  
{
    DMA3CTL = DMADT_0 | DMADSTINCR_3 | DMASRCINCR_0 | DMADSTBYTE | DMASRCBYTE ;
    DMA3CTL |= DMAEN;
    MCP3561_Read(MCP3561_Data.adcdata,IREAD_COMMAND,4); 
}