基于 qemu 的 riscv32架构的 非官方rt-thread 体验 教程

主机环境: ubuntu-20.04.3-desktop-amd64.iso
安装包 : sudo apt-get install net-tools openssh-server git vim make gcc gawk  bison flex  texinfo automake  libtool-bin cvs libncurses5-dev ninja-build libglib2.0-dev libpixman-1-dev help2man

编译器 :
	sifive 提供的 
		riscv64-unknown-elf-gcc-8.3.0-2020.04.1-x86_64-linux-ubuntu14.tar.gz或
		riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz
仿真器 :
	qemu-6.1.0 自己编译 出 qemu-system-riscv32
rt-thread代码:
	https://gitee.com/bigmagic/riscv32_rtt/

1. 编译器准备

在 https://github.com/sifive/freedom-tools/releases 下载
riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz 或
riscv64-unknown-elf-gcc-8.3.0-2020.04.1-x86_64-linux-ubuntu14.tar.gz

2. 仿真器准备

// 配置
qemu-6.1.0$./configure --target-list=riscv32-softmmu,riscv64-softmmu --prefix=/home/pop/work/qemu/qemu-out   2>&1 | tee log_configure.txt
// 编译
make 2>&1 | tee log_build.txt
// 安装
make install 2>&1 | tee log_install.txt
// 测试

pop@ubuntu:~$ qemu-system-riscv32 -machine help
Supported machines are:
none                 empty machine
opentitan            RISC-V Board compatible with OpenTitan
sifive_e             RISC-V Board compatible with SiFive E SDK
sifive_u             RISC-V Board compatible with SiFive U SDK
spike                RISC-V Spike board (default)
virt                 RISC-V VirtIO board
pop@ubuntu:~$ qemu-system-riscv64 -machine help  
Supported machines are:
microchip-icicle-kit Microchip PolarFire SoC Icicle Kit
none                 empty machine
shakti_c             RISC-V Board compatible with Shakti SDK
sifive_e             RISC-V Board compatible with SiFive E SDK
sifive_u             RISC-V Board compatible with SiFive U SDK
spike                RISC-V Spike board (default)
virt                 RISC-V VirtIO board

3.代码准备并编译

git clone https://gitee.com/bigmagic/riscv32_rtt.git // 当前 commit id 为 ff43c3e025355f1807cf75ff6e4512e493ec4acf
cd riscv32_rtt/bsp/riscv32-virt
// change riscv32_rtt/bsp/riscv32-virt/rtconfig.py
// EXEC_PATH   = r'/home/pop/work/freertos-riscv/riscv64-unknown-elf-gcc-8.3.0-2020.04.1-x86_64-linux-ubuntu14/bin'
scons --target=makefile
make
编译成功,会生成 riscv32_rtt/bsp/riscv32-virt/rtthread.elf

4. 仿真器加载 rtthread镜像

qemu-system-riscv32 -M virt -kernel rtthread.elf -nographic
打印如下

OpenSBI v0.9
   ____                    _____ ____ _____
  / __ \                  / ____|  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |____) | |_) || |_
  \____/| .__/ \___|_| |_|_____/|____/_____|
        | |
        |_|

Platform Name             : riscv-virtio,qemu
Platform Features         : timer,mfdeleg
Platform HART Count       : 1
Firmware Base             : 0x80000000
Firmware Size             : 100 KB
Runtime SBI Version       : 0.2

Domain0 Name              : root
Domain0 Boot HART         : 0
Domain0 HARTs             : 0*
Domain0 Region00          : 0x80000000-0x8001ffff ()
Domain0 Region01          : 0x00000000-0xffffffff (R,W,X)
Domain0 Next Address      : 0x80200000
Domain0 Next Arg1         : 0x87000000
Domain0 Next Mode         : S-mode
Domain0 SysReset          : yes

Boot HART ID              : 0
Boot HART Domain          : root
Boot HART ISA             : rv32imafdcsu
Boot HART Features        : scounteren,mcounteren,time
Boot HART PMP Count       : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 32
Boot HART MHPM Count      : 0
Boot HART MHPM Count      : 0
Boot HART MIDELEG         : 0x00000222
Boot HART MEDELEG         : 0x0000b109
heap: [0x80e00000 - 0x81600000]

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