module LED( clk,led );//clk是50MHz的晶振产生的信号
input clk;
output[3:0] led;
reg[25:0] count;
reg[3:0] led;
always@(posedge clk)
begin
count<=count+1;
if(count==25'd25000000)
begin
led<=~led;
count<=0;
end
end
endmodule
FPGA 闪烁LED
最新推荐文章于 2024-05-21 14:59:29 发布