FPGA LED闪烁

要求：开发板四个LED以1ms依次闪烁

`timescale 1ns/1ps

module led_text(  
						clk,  //开发板的时钟50Mhz
						rst_n,
						led
    );

input clk;
input rst_n;
output [3:0] led;

reg[31:0] timer;   //计数寄存器
reg[3:0] led;

always @(posedge clk or negedge rst_n)
		begin 
			if (~rst_n)    //复位信号低电平有效
				timer <=0;
			else if (timer==32'd199_999)
				timer <=0;
			else
				timer<=timer+1'b1;
			end
always @(posedge clk or negedge rst_n)
		begin 
			if (~rst_n)
				led <= 4'b1111;  //led低电平有效
			else if (timer==32'd49_999)
				led <= 4'b0111;
			else if  (timer==32'd99_999)
				led <= 4'b1011;
			else if (timer==32'd149_999)
				led <= 4'b1101;
			else if (timer==32'd199_999)
				led <= 4'b1110;
			else
				led <= led ;
			end
			
endmodule

module vtf_led_text;

	// Inputs
	reg clk;
	reg rst_n;

	// Outputs
	wire [3:0] led;

	// Instantiate the Unit Under Test (UUT)
	led_text uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.led(led)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst_n = 0;

		// Wait 100 ns for global reset to finish
			#100;
			rst_n = 1;
			#6000000;
			rst_n = 0;
			#1000000;
			rst_n = 1;
			//#2000;
		//$stop;
        
		// Add stimulus here

	end
	always #10 clk=~clk;   //50Mhz时钟源
	   
endmodule