hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/Simple FSM 2(asynchronous reset)

最新推荐文章于 2024-08-05 13:24:32 发布

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最新推荐文章于 2024-08-05 13:24:32 发布

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module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        // State transition logic
        if((j==0) && (k==0))
            next_state = state;
        else if ((j==1) && (k==1))
            next_state = !state;
        else if ((j==1) && (k==0))
            next_state = ON;
        else // 
            next_state = OFF;
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset )
            state = OFF;
        else begin
            state = next_state;
        end
    end

    // Output logic
    // assign out = (state == ...);
    assign out = (state == ON)? 1: 0;

endmodule