module top_module(
input clk,
input in,
input areset,
output out); //
reg [3:0] state, next_state;
parameter A = 4'b0001;
parameter B = 4'b0010;
parameter C = 4'b0100;
parameter D = 4'b1000;
// State transition logic
always @(*) begin
next_state = A;
case (state)
A: begin
if(in)
next_state = B;
else
next_state = A;
end
B: begin
if(in)
next_state = B;
else
next_state = C;
end
C: begin
if(in)
next_state = D;
else
next_state = A;
end
D: begin
if(in)
next_state = B;
else
next_state = C;
end
default: begin
next_state = A;
end
endcase
end
// State flip-flops with asynchronous reset
always @(posedge clk, posedge areset) begin
if(areset)
state = A;
else
state = next_state;
end
// Output logic
always @(*) begin
if(state == D)
out = 1;
else
out = 0;
end
endmodule
hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/Simple FSM 3(asynchronous reset)
最新推荐文章于 2024-06-07 23:09:19 发布