hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/Simple FSM 1(asynchronous reset)

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        // State transition logic
        if(in == 1) 
            next_state = state;
        else if(in == 0) begin 
            if (state == A)
                next_state = B;
            else if (state == B)
                next_state = A;
        end
            
    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if(areset)
            state = B;
        else 
            state = next_state;
    end

    // Output logic
        assign out = (state == A)? 0: 1;

endmodule

状态转换写在边沿里, 也可以通过验证

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        // State transition logic
        state = next_state;
    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if(areset) begin
            next_state = B;
        end
        else if(in == 0) begin
            if(state == A)
                next_state = B;
            else
                next_state = A;
        end
    end

    // Output logic
    // assign out = (state == ...);
    assign out = (state == B)? B: A;

endmodule