module top_module(
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err);
parameter NONE = 10'b0000000001;
parameter ONE = 10'b0000000010;
parameter TWO = 10'b0000000100;
parameter THREE = 10'b0000001000;
parameter FOUR = 10'b0000010000;
parameter FIVE = 10'b0000100000;
parameter SIX = 10'b0001000000;
parameter ERROR = 10'b0010000000;
parameter DISCARD = 10'b0100000000;
parameter FLAG = 10'b1000000000;
reg [9:0] state, next;
//ff
always @(posedge clk) begin
if(reset)
state = NONE;
else
state = next;
end
//trans
always @(*) begin
case (state)
NONE: begin
if(in)
next = ONE;
else
next = NONE;
end
ONE: begin
if(in)
next = TWO;
else
next = NONE;
end
TWO: begin
if(in)
next = THREE;
else
next = NONE;
end
THREE: begin
if(in)
next = FOUR;
else
next = NONE;
end
FOUR: begin
if(in)
next = FIVE;
else
next = NONE;
end
FIVE: begin
if(in)
next = SIX;
else
next = DISCARD;
end
SIX: begin
if(in)
next = ERROR;
else
next = FLAG;
end
ERROR: begin
if(in)
next = ERROR;
else
next = NONE;
end
DISCARD: begin
if(in)
next = ONE;
else
next = NONE;
end
FLAG: begin
if(in)
next = ONE;
else
next = NONE;
end
default:
next = NONE;
endcase
end
//out
assign disc = (state == DISCARD)? 1'b1: 1'b0;
assign flag = (state == FLAG )? 1'b1: 1'b0;
assign err = (state == ERROR )? 1'b1: 1'b0;
endmodule
hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/Sequence recognition
最新推荐文章于 2023-09-24 00:12:58 发布