Verilog两种方式实现2-4译码器

in0	in1	out0	out1	out2	out3
0	0	0	1	1	1
0	1	1	0	1	1
1	0	1	1	0	1
1	1	1	1	1	0

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2-4译码器真值表

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2-4译码器电路图

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 module decoder2_4(in0,in1,en,out0,out1,out2,out3);//调用门级元件实现2-4译码器
     input in0,in1,en;
     output out0,out1,out2,out3;
     wire wire1,wire2;
     not U1(wire1,in0),
          U2(wire2,in1);
     nand U3(out0,en,wire1,wire2),
           U4(out1,en,wire1,in1),
           U5(out2,en,in0,wire2),
           U6(out3,en,in0,in1);
 endmodule

 module decoder2_4(in0,in1,en,out0,out1,out2,out3);//连续赋值语句实现2-4译码器
     input in0,in1,en;
     output out0,out1,out2,out3;
     wire wire1,wire2;
     assign wire1 = !in0;
     assign wire2 = !in1;
     assign out0 = !(wire1 & wire2 & en);
     assign out1 = !(wire1 & in1 & en);
     assign out2 = !(wire2 & in0 & en);
     assign out3 = !(in0 & in1 & en);
 endmodule

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验证结果

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