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错误的状态机图：

正确的状态机图：

3#bit应该去检查是不是0， 如果是0，往前走， 如果是1， 这个新的1成为了2#bit的1， 继续等一个0.

代码：

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);
    
    parameter C1 = 5'd1;
    parameter C2 = 5'd2;
    parameter C3 = 5'd3;
    parameter C4 = 5'd4;
    parameter END = 5'd5;
    
    reg [4:0] state, next;
    
    //ff
    always @(posedge clk) begin
        if(reset)
            state = C1;
        else
            state = next;
    end
    
    //trans
    always @(*) begin
        if(reset)
            next = C1;
        else begin
            case(state)
                C1:begin
                    if(data==1)
                        next = C2;
                    else
                        next = C1;
                end
                C2:begin
                    if(data==1)
                        next = C3;
                    else
                        next = C1;
                end
                C3:begin
                    if(data==0)
                        next = C4;
                    else
                        next = C3;
                end
                C4:begin
                    if(data==1)
                        next = END;
                    else
                        next = C1;
                end
                END:
                    next = END;
                default:
                    next = C1;
            endcase
        end
    end
    
    //out
    assign start_shifting = (state==END)? 1'b1: 1'b0;

endmodule