3 APB-Matrix 测试点梳理

1. DUT 是哪种类型？不同类型的测试点如何梳理？

2.0 处理器 (TO-DO)

2.1 总线协议类 (cookbook, APB3)

APB3 procotol testplan:

section	description	coverage type	priority
unknown signal valu checks
PRESETn	be always in a known state.	asserion	1
PSEL		asserion	1
Timing relationship checks
Other checks
functinal coverage

2.2 高速接口 (TO-DO)

2.3 低速接口

1) 低速概念？uart 速率，I2C 速率？

uart 速率与收发器对数有关，RS232/422/485 ,不同标准支持速率不同，112.5kbps ~ 10Mbps（参考博文）

I2C 速率通常由控制 SCL 信号线的主设备决定，不同模式速率不同，100kbps ~ 5Mbps （参考博文）

2) uart 验证点 (cookbook)

section	desciption	coverage type	priority
寄存器
Reset values	registers return the specified reset values	test result	1
register accesses	all registers been accessed for all possible access modes	covergroup, cross	1
bit level register access	all r/w bits in the registers toggle correctly	test result	1
APB protocol	APB protocol has been tested in all modes	APB monitor	1
发送器
character formats	all possible character formats are transmitted correctly	covergroup, cross	1
TX FIFO empty flag	when the fifo is empty, the fifo empty flag is set; and is read back correctly	assertion, covergroup	1
TX empty flag	the ransmit empty flag is set correctly and is read back correctly	assertion, covergroup	1
接收器
character formats	all possible character formats are received correctly	covergroup, cross	1
data received flag	the flag is set when data is available and read back correctly	assertion, covergroup	1
RX Line Status
framing error	framing errors are detected for one/two stop bits	assertion, covergroup	2
parity error	parity errors are deteced for all types of parity	assertion, covergroup	1
break indication	a break condition is detected correctly for all character formats	covergroup, cross	2
overrun error	rx overrun is detected for all character formats	covergroup, cross	2
FIFOE	FIFO Error condition is valid for all error/indcation type	covergroup, cross	2
Status	any valid combination of error/indicator has been observed	covergroup, cross	2
Moderm interface
moderm outputs	all combinations of moderm output have been seen	covergroup, cross	3
moderm inputs	1. all combination of modem input values have been seen 2. the moderm input status change signals work correctly.	1. covergroup cross; assertion, covergroup	3
loopback mode		covergroup	2
中断
interrupt enable	all combinations of the interrupt enable bits have been used	covergroup, cross	1
interrupt ID	all valid interrupt IDs have been detected	covergroup, cross	1
receive FIFO interrupt	1. seen for all possible character formats 2. all possible RX FIFO threshold values checked.	covergroup, cross	2
rx line status interrupt	interrupts generated for all possible combinations of errors and indicators for all character formats.	covergroup, cross	1
transmit empty interrupt	generated for all character formats	covergroup, cross	1
modem status interrupt	generated for all combinations of the signal change bits	covergroup, cross	3
receive timeout interrupt	check for the shortest and longest character format and 4 other formats	covergroup	4
波特率
divider values	1. check uart operation for a range of baud rate divider values 2. check baud rate divider ratio for a selection of values via baud rate divider output	covergroup	2
code coverage
statement coverage
branch coverage
FSM coverage

4) 数据流处理 (TO-DO, UART/I2C?)

5) 算法处理模块 (cookbook, TO-DO)

2. AHB-Matrix 测试计划表格整理

2.1 参考哪些 input，梳理测试点

<apb_databook> function description； coreconsult configuration.

2.2 测试计划表格

Section	description	covertype	priority
寄存器
接口（数据传输）
地址范围
仲裁
中断

3 重点

3.1 Register description

Register	Offset	bits	Description
AHB_PL1	0x0100_0000	32	[3:0] ; arbitration priority for master 1 register used for programming the AHB master 1 priority
AHB_PL2	0x0100_0004	32	[3:0] ; arbitration priority for master 2
AHB_PL3	0x0100_0008	32	[3:0] ; arbitration priority for master 3
AHB_EBTCOUNT	0x0100_003c	32	[9:0] ; Early burst termination count register. Maximum number of cycles a transfer can take before being subject to an early burst termination.
AHB_EBT_EN	0x0100_0040	32	0; Early burst termination enable is to enable or disable EBT through the software programming
AHB_EBT	0x0100_0044	32	0; Early burst termination register. Set when an Early Burst Termination takes place. The register is cleared when read by the processor.
AHB_DFLT_MASTER	0x0100_0048	32	[3:0] ; Default manager ID number register. The default manager is the manager that is granted by the bus when no manager has requested ownership.
AHB_VERSION_ID	0x0100_0090	32	This register provides the component version ID.

3.2 EBT (Early Burst Termination)

TO-DO