verilog任意整数分频的实现

波形

代码

`timescale 1ns/10ps
module divn_tb;
reg clk;
reg rst_n;
reg [31:0] div;
wire o_clk;

divn u0 (
.clk(clk),
.rst_n(rst_n),
.div(div),
.o_clk(o_clk)
);


initial begin
clk   = 1'b1;
div   = 32'h5;
rst_n = 1'b0;

   #50 rst_n = 1'b1;
#1000;
end


always #10 clk = ~clk;
endmodule







module divn    (
input clk,
input rst_n,
input [31:0] div,
output o_clk
);

parameter WIDTH = 32;

reg [WIDTH-1:0] cnt_p;
reg [WIDTH-1:0] cnt_n;
reg             clk_p;
reg             clk_n;

assign o_clk = (div == 1) ? clk :
               (div[0])   ? (clk_p | clk_n) : (clk_p);

always@(posedge clk or negedge rst_n) begin
if (!rst_n)
    cnt_p <= 0;
else if (cnt_p == (div-1))
    cnt_p <= 0;
else
    cnt_p <= cnt_p + 1;
end

always@(posedge clk or negedge rst_n) begin
if (!rst_n) 
    clk_p <= 1;
else if (cnt_p < (div>>1))
    clk_p <= 1;
else
    clk_p <= 0;    
end

always@(negedge clk or negedge rst_n) begin
if (!rst_n)
    cnt_n <= 0;
else if (cnt_n == (div-1))
    cnt_n <= 0;
else
    cnt_n <= cnt_n + 1;
end

always@(negedge clk or negedge rst_n) begin
if (!rst_n)
    clk_n <= 1;
else if (cnt_n < (div>>1))
    clk_n <= 1;
else
    clk_n <= 0;
end

endmodule