VHDL 的UART 的实现

今天闲来无事甚是无聊，就写两篇博客打发时间吧···

     这篇博客首先介绍UART基本的原理，接下来就贴出我得代码。

     UART是一个串行的数据传输格式，发送和接收分别只使用一根信号线。在低速率的信号传输时常常会使用到，但是在高速数据传输的时候就得需要改变传输方式，比如使用MAC ETHERNET 来完成。

     言归正传，首先我UART发送/接收数据的格式是：一个起始位(0)，8个数据位，一个停止位(1)。当TX/RX上没有数据传输时，信号线置1。

   

    程序有3个子模块，分别是发送，接收和波特率产生。

    下面贴出代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity baud is --分频9600*16
    Port (clk :in  std_logic;
	       bclk:out std_logic);
end baud;
architecture Behavioral of baud is
begin
process(clk)
variable cnt:integer;
begin                           
  if rising_edge(clk) then
     if cnt>=325 then cnt:=0; bclk<='1';                        --设置分频系数305ori
	 else cnt:=cnt+1; bclk<='0';
	 end if;
  end if;
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity baud2 is                 --分频9600
    Port (clk :in  std_logic;
	       bclk:out std_logic);
end baud2;
architecture Behavioral of baud2 is
begin
process(clk)
variable cnt:integer:=0;
begin                           
  if rising_edge(clk) then
     if cnt>=5208 then cnt:=0; bclk<='1';                        --设置分频系数206
	 else cnt:=cnt+1; bclk<='0';
	 end if;
  end if;
end process;
end Behavioral;

发送模块

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TX2 is
	port(
		BAUD :in  std_logic;
		EN   :in  std_logic;
		BUF  :in  std_logic_vector(7 downto 0);
		TXD  :out std_logic
	);
end TX2;

architecture BV of TX2 is
begin

	process(BAUD)
   	variable cnt :integer:= 0;
	begin
--		if EN = '1' then 
		  if rising_edge(BAUD) then
			  case cnt is
			  	  when 0 => TXD<='0'; cnt:=cnt+1;
				  when 9 => TXD<='1'; cnt:=0;
				  when others => TXD <=BUF(cnt-1); cnt:=cnt+1;   
			  end case;
		  end if;
	--	else
	--		TXD <='1';

--		end if;
		
	end process;
	
end architecture;

接收模块

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RX is
generic(framlenr:integer:=8);	         
    Port (bclkr,resetr,rxdr:in std_logic;                        
	     r_ready:out std_logic;
		 rbuf:out std_logic_vector(7 downto 0));
end RX;
architecture Behavioral of RX is
type states is (r_start,r_center,r_wait,r_sample,r_stop);         
signal state:states:=r_start;
signal rxd_sync:std_logic;
begin
pro1:process(rxdr)
begin
  if rxdr='0' then rxd_sync<='0';
  else rxd_sync<='1';
  end if;
end process;

pro2:process(bclkr,resetr,rxd_sync)                           
variable count:std_logic_vector(3 downto 0);                     
variable rcnt:integer:=0;
variable rbufs:std_logic_vector(7 downto 0);
begin
  if resetr='1' then state<=r_start; count:="0000";                
  elsif rising_edge(bclkr) then
     case state is
	   when r_start=>                                      
if rxd_sync='0' then state<=r_center; r_ready<='0'; rcnt:=0;
			else state<=r_start; r_ready<='0';
			end if;                              
when r_center=>                                     
if rxd_sync='0' then
			    if count="0100" then state<=r_wait; count:="0000";
else count:=count+1; state<=r_center;
end if;
			else state<=r_start;
			end if;                            
when r_wait=>                                       
if count>="1110" then
if rcnt=framlenr then state<=r_stop;
			    else state<=r_sample;
			    end if;
			count:="0000";                    
		    else count:=count+1; state<=r_wait;
			end if;
when r_sample=>rbufs(rcnt):=rxd_sync; rcnt:=rcnt+1;state<=r_wait;
                                                   
       when r_stop=>r_ready<='1'; rbuf<=rbufs; state<=r_start;  
       when others=>state<=r_start;
     end case;
  end if;
end process;
end Behavioral;

由此可以看出，做发射部分容易，但是实现接收比较复杂。