Lemmings2 Verilog代码

Lemmings2 Verilog代码
题目来源 ：Lemmings2

代码如下：

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
    
    parameter WL=0,WR=1,FALL=2;
    reg  [1:0] sta,next,pre;//,r_walk_left,r_walk_right,r_aaah;
    reg r_ground;
    wire f_ground;
    
    always@(*)
        case(sta)
            WL: next = ground ? (bump_left ? WR : WL) : FALL; 
            WR: next = ground ? (bump_right? WL : WR) : FALL; 
            FALL: next = ground ? pre : FALL; 
        endcase
    
    always@(posedge clk or posedge areset)
        if(areset) sta <= WL;
        else sta <= next;
    
    always@(posedge clk or posedge areset)
         if(areset) r_ground <= 1;
         else r_ground <= ground;
    
    assign f_ground = !ground & r_ground;
    
    always@(posedge clk or posedge areset)
        if(areset)
            pre <= WL;
       else if(f_ground)
            pre <= sta;
   
        
    assign aaah = sta == FALL;
    assign walk_left = sta == WL;
    assign walk_right = sta == WR;

endmodule