Lemmings4 verilog代码

Lemmings4 verilog代码
题目来源：Lemmings4

代码如下：

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    
    parameter WL=0,WR=1,FALL=2,DIG=3,SPLA=4;
    reg  [2:0] sta,next,pre,pre2;
    reg r_ground;
    wire f_ground,splatter;
    reg  [4:0] fall_count;
    
    always@(*)
        case(sta)
            WL: next = ground ? (dig ? DIG : bump_left ? WR: WL) : FALL; 
            WR: next = ground ? (dig ? DIG : bump_right? WL: WR) : FALL; 
            FALL: next = ground ? (splatter ? SPLA : pre ): FALL; 
            DIG:  next = ground ? DIG : FALL; 
        endcase
    
    always@(posedge clk or posedge areset)
        if(areset) sta <= WL;
        else sta <= next;
    
    always@(posedge clk or posedge areset)
         if(areset) r_ground <= 1;
         else r_ground <= ground;
    
    assign f_ground = !ground & r_ground;
    
    always@(posedge clk or posedge areset)
        if(areset)
            pre <= WL;
    else if(f_ground)
            pre <= sta == DIG ? pre2 : sta;
   
    always@(negedge clk or posedge areset)
        if(areset)
            pre2 <= WL;
    else if(sta != DIG )
            pre2 <= sta;
    
    always@(posedge clk or posedge areset)
        if(areset)
            fall_count <= 5'h0;
        else if(sta == FALL)
            fall_count <= fall_count >= 20 ? fall_count : fall_count + 5'h1;
        else
            fall_count <= 5'h0;
    
    assign splatter = fall_count >= 20; 
    assign aaah = sta == FALL;
    assign walk_left = sta == WL;
    assign walk_right = sta == WR;
    assign digging = sta == DIG;

endmodule