本文仅以 active high clock gating cell 为讨论目标
常见的ICG 模型如下
Negative level sensitive latch + AND
module (
//input
input wire EN,
input wire D,
output wire gclk
);
reg GCLK;
always @(EN or D) begin
if (~EN)
GCLK = D; //blocking assignment
end
assign gclk = GCLK & EN;
endmodule
事实上,Negative Edge triggered DFF + AND 也有等价的时序, 只不过后者常常会多出一个rst_n pin
module icg_dff (//
input wire clk,
input wire rst_n,
input wire d,
output wire gclk
);
reg q;
always @(negedge clk or negedge rst_n) begin
if (~rst_n)
q<= 1'b0;
else
q<= d;
end
assign gclk = q&&clk;
endmodule
从简单的仿真结果来看,也能说明两者功能上是相同的
//testbench
`timescale 1ns/1ps
module tb();
reg clk;
reg rstn;
reg enable;
initial begin
clk = 0;
rstn = 0;
enable = 0;
@(posedge clk);
#0.05 rstn = 1;
@(posedge clk);
#1 enable = 1;
repeat (5) @(posedge clk);
@(posedge clk);
#1 enable = 0;
repeat (5) @(posedge clk);
@(posedge clk);
#1 enable = 1;
@(posedge clk);
#1 enable = 0;
#50 $finish;
end
always #5 clk = ~clk;
icg_user icg_00 (//
.EN(enable),
.CLK(clk),
.gclk(gclk));
icg_dff u_icg_dff (//
.clk(clk),
.rst_n(rstn),
.d(enable),
.gclk(gclk_dff)
);
endmodule