VHDL 进程间的数据传递规则

“在VHDL中不允许在两个进程中同时对同一个信号进行赋值”，下面我们通过两个实例具体来解释一下这句话。

ENTITY sort IS
   PORT (
      
      clk   : IN STD_LOGIC;
      rst   : IN STD_LOGIC;
      out0  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

   );
END sort;
ARCHITECTURE trans OF sort IS
begin
   PROCESS (clk)
   BEGIN
      IF (clk'EVENT AND clk = '1') THEN
         IF (rst = '1') THEN
            out0 <= "00000000";
         else
            ..................
            ..................
            ..................
         end if;

      end if;
   end process;

    process(clk)
    begin
      IF (clk'EVENT AND clk = '1') THEN
         IF (out_start = '1') THEN
            out0 <= out_temp(0);
            ................
            ................
            ................
         end if;
      end if;
    end process;

以上这段代码是对输出信号的操作，第一个进程（process）中是对输出信号