前面写过一个74ls165并转串的程序,但实际用了2块165级联成16位的并转串,为了布线是的方便,就把并行输入的数据打乱了,现在要调整回去,可以借鉴下面的程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity swap is port ( data :in std_logic_vector(7 downto 0); q :out std_logic_vector(7 downto 0) ); end entity; architecture rtl of swap is procedure swap1(a :inout std_logic_vector(7 downto 0))is variable temph,templ :std_logic_vector(3 downto 0); begin templ:=a(3 downto 0); temph:=a(7 downto 4); a:=templ&temph; end swap1; begin process(data) variable b:std_logic_vector(7 downto 0); begin b:=data; swap1(b); q<=b; end process; end rtl; 仿真结果 PS:还有些其他的问题没有像明白,慢慢想了