看公司的vhdl代码大部分都是用状态机来完成的,看的很有条理,一个状态一个状态的来,工作过程看的一清二楚 我写的很简单,也很丑陋,慢慢进步了 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity test is port( sw :in std_logic_vector(3 downto 0); clk,reset :in std_logic; led :out std_logic_vector(3 downto 0)--对应于输出的一些指示 ); end test; architecture rtl of test is type state is (idle,s1,s2,s3); signal tmp :state; begin process(clk,reset) begin if reset='0' then tmp<=idle; -- led<="1111"; --这里不能加上,不然仿真时,对应的输出是红线,不清楚为什么 elsif clk'event and clk='1' then case tmp is when idle => if sw(1)='1' then tmp<=s1; else tmp<=idle; end if; when s1 => if sw(2)='1' then tmp<=s2; else tmp<=idle; end if; when s2 => if sw(3)='1' then tmp<=s3; else tmp<=idle; end if; when s3 => if sw(3)='1' then tmp<=s3; else tmp<=idle; end if; end case; end if; end process; process(tmp) begin case tmp is when idle=> led<="0001"; when s1=> led<="0010"; when s2=> led<="0100"; when s3=> led<="1000"; end case; end process; end rtl; 仿真图如下: