计数器的 VHDL 程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY a2 IS
PORT(CLK:IN STD_LOGIC;
     Q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END a2;
ARCHITECTURE b2 oF a2 IS
SIGNAL Qtmp:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
 PROCESS(CLK)
  BEGIN
   IF CLK' EVENT AND CLK='1' THEN
    Qtmp <= Qtmp+1;
   END IF;
 Q <=Qtmp;
END PROCESS;
END b2;