四选一选择器的 VHDL程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY a1 IS
 PORT(A,B,C,D,S1,S0:IN STD_LOGIC;
                  Y:OUT STD_LOGIC);
END a1;
ARCHITECTURE b1 OF a1 IS
 SIGNAL SS:STD_LOGIC_VECTOR (1 DOWNTO 0);
 BEGIN
   PROCESS(A,B,C,D,S1,S0)
    BEGIN
     SS<=S1&S0;
      CASE SS IS
       WHEN"00"=>Y<=A;
       WHEN"01"=>Y<=B;
       WHEN"10"=>Y<=C;
       WHEN"11"=>Y<=D;
       WHEN OTHERS=>NULL;
      END CASE;
   END PROCESS;
END b1;