verilog从txt中读取_在Verilog中从txt读取和写入

First of all I want to say that I'm running the simulation in ADS (Advanced Design System 2017) through a Verilog model compiled in ModelSim.

My objective is loading data from a .txt file into the testbench as input in order to run the simulation, and afterwards save the results of this simulation in another .txt file.

Here is the content for the input test .txt file called "param.txt":

1

2

3

4

5

And here is my Verilog testbench code:

`include "disciplines.vams"

module resistor(p,n);

electrical p,n;

parameter real R=50.0;

integer file;

integer out;

real pwm_A[0:10];

integer i;

integer count;

analog begin

@(initial_step) // Initial Conditions

begin

// Read

file=$fopen("para