看FPGA面试题时见到被考到的几个逻辑电路

8位 D触发器：

 1 module dff8(clk , reset, d, q);
 2 input        clk;
 3 input        reset;
 4 input  [7:0] d;
 5 output [7:0] q;
 6 reg   [7:0] q;
 7 always @ (posedge clk or posedge reset)
 8    if(reset)
 9      q <= 0;
10    else
11      q <= d;
12 endmodule

 

D触发器实现2分频：

 1 module divide2( clk , clk_o, reset);
 2    input     clk , reset;
 3    output   clk_o;
 4    wire in; 
 5 reg out ;
 6    always @ ( posedge clk or posedge reset)
 7      if ( reset)
 8        out <= 0;
 9          else
10            out <= in;
11        assign in = ~out;
12        assign clk_o = out;
13      endmodule

 

转载于:https://www.cnblogs.com/fallenmoon/p/7464203.html