初分配和再分配图解_电荷再分配型SAR ADC

本文详细介绍了SAR ADC的工作流程,包括下极板采样和上极板采样的区别。在下极板采样中,电荷通过逐次比较和再分配来确定模拟信号的数字值,而在上极板采样中,虽然存在精度影响,但功耗更低。此外,还讨论了采样保持电路、比较器和SAR逻辑控制电路的关键作用。
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1.基础理论

为了把模拟信号数字化,前辈们发明很多ADC,flash ADC、delta-sigma、pipeline ADC、SAR ADC. successive-approximation register (SAR) analog-to-digital converters (ADCs)是常规的ADC的类型,因为它的高精度低功耗速度快的所以广泛的应用于生物芯片,IOT终端等多个领域。

SAR ADC 主要包括采样保持电路(S/H),比较器(Comparator,COMP),SAR 逻辑控制电路以及数模转换(Digitalto Analog Converter,DAC)电路。

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SAR ADC 基本电路

简单介绍一下SAR ADC的工作流程,SAR ADC就是逐次把信号和DAC的值进行比较,最后得到一个精确的值。

1.下极板采样SAR ADC.

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This dissertation proposes three circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-of-concept prototypes, the proposed techniques are able to improve the operating speed and achieve excellent energy efficiency. The proposed techniques and chip measurement results are sketched as follows: The first technique is a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total sampling capacitance are reduced by about 81.3% and 50%, respectively. A 10-bit, 50-MS/s SAR ADC with the proposed monotonic capacitor switching procedure is implemented in a 0.13-μm 1P8M CMOS technology. The prototype ADC consumes 0.92 mW from a 1.2-V supply, and the effective number of bit (ENOB) is 8.48 bits. The resulting figure of merit (FOM) is 52 fJ/conversion-step. However, the signal-dependent offset caused by the variation of the input common-mode voltage degrades the linearity of ADC. We proposed an improved comparator design to avoid the linearity degradation. Besides, to avoid a clock signal with frequency higher than sampling rate, we used an asynchronous control circuit to internally generate the necessary control signals. The revised prototype is also implemented in a 0.13-μm 1P8M CMOS technology. It consumes 0.826 mW from a 1.2-V supply and achieves an ENOB of 9.18 bits. The resultant FOM is 29 fJ/conversion-step.
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