经典设计整理之一——————获取信号的上升沿和下降沿

有的时候需要获取信号的上升沿或下降沿，如延时消抖。在此特准备了一个简单的代码，以便以后用。

获取上升沿和下降沿代码：

 1 /*********************************************************************************
 2     Company:        
 3     Engineer:            中华小虾
 4     Project Name:    
 5     Module Name:    acq_edge.v
 6     Function Description:捕捉上升沿和下降沿
 7             
 8     Revision History: 
 9             v1.0     2013.3.17      Description: Initial Release.
10 ***********************************************************************************/
11 
12 module acq_edge(clk,rst_n,signal,pos_edge,neg_edge);
13 
14     input clk;
15     input rst_n;
16     input signal;
17     output pos_edge;
18     output neg_edge;
19     
20     reg [1:0] acq;
21     
22     always @(posedge clk or negedge rst_n)
23     begin
24         if(!rst_n)
25             acq <= 0;
26         else
27             acq <= {acq[0],signal};
28     end 
29     
30     assign pos_edge = ~acq[1] & acq[0];            //捕捉上升沿
31     assign neg_edge = acq[1] & ~acq[0];            //捕捉下升沿
32     
33 endmodule 

 

测试文件：

 1 /*********************************************************************************
 2     Company:        
 3     Engineer:            中华小虾
 4     Project Name:    
 5     Module Name:    edge_tb.v
 6     Function Description:测试acq_edge.v
 7             
 8     Revision History: 
 9             v1.0     2013.3.17      Description: Initial Release.
10 ***********************************************************************************/
11 
12 module edge_tb;
13 
14     reg     clk;
15     reg     rst_n;
16     reg     signal;
17     wire     pos_edge;
18     wire     neg_edge;
19     
20     acq_edge unit(
21                         .clk(clk),
22                         .rst_n(rst_n),
23                         .signal(signal),
24                         .pos_edge(pos_edge),
25                         .neg_edge(neg_edge)
26                     );
27 
28 //设置监视信号
29     initial
30     begin
31         $monitor ($time,"pos_edge = %b, neg_edge = %b", pos_edge,neg_edge);
32     end
33                     
34 //设置时钟
35     initial
36     begin
37         clk = 0;
38         forever #5 clk = ~clk;                //设clk为100MHz
39     end
40     
41 //控制清零信号
42     initial
43     begin
44         rst_n = 0;                            
45         repeat (5) @(negedge clk);
46         rst_n = 1;
47     end
48                 
49 //施加激励信号
50     initial
51     begin
52         signal = 0;
53         repeat (10) @(negedge clk);    signal = 1;
54         repeat (1) @(negedge clk);    signal = 0;    
55         repeat (10) @(negedge clk);    signal = 1;
56         repeat (10) @(negedge clk);    signal = 0;
57         repeat (1) @(negedge clk);    signal = 1;
58         repeat (5) @(negedge clk);    signal = 0;
59         
60         repeat (10) @(negedge clk);    $stop;
61         
62     end
63                 
64 endmodule                

 

Isim仿真：

转载于:https://www.cnblogs.com/zhonghuaxiaoxia/archive/2013/03/17/2964841.html