FIFO FWFT Write or Read 时序图

图中wr_en 信号 和 empty是同一信号， 当复位后写入3个数据后，empty信号才变为假

测试代码

`timescale 1ns / 1ps
module test (    
    input   wire     clk,
    input   wire     srst    
   );
   wire                  clk_50m;
   wire   [8:0]          data_count;
   wire   full, empty;
   reg    [15:0]         din;
   reg                   wr_en,rd_en;
   wire   [15:0]         dout;
   reg    [15:0]         data_cnt;
   always @(  posedge clk  or posedge  srst ) begin
       if(srst) begin
               wr_en <= 0;
               rd_en <= 1;
               din   <= 5;  
               data_cnt <= 0;            
       end else begin
               din <= din + 1;
       end
   end
   fifo_common_clk  my_com_clk_fifo(
        .clk(clk),                    // input wire clk
        .srst(srst),                // input wire srst
        .din( din ),                      // input wire [15 : 0] din
        .wr_en( empty ),                  // input wire wr_en
        .full( full ),                    // output wire full
        .rd_en( rd_en ),                  // input wire rd_en
        .dout( dout ),                    // output wire [15 : 0] dout        
        .empty( empty ),                   // output wire empty
        .data_count(data_count)            // output wire [8 : 0] data_count
   );
endmodule

仿真代码

`timescale   1ns / 1ps
module tb(  );
reg  clk_50M;
reg rst;
initial begin
clk_50M = 0;
rst = 1;    
#80   rst = 0;
#2000 $stop;
end 
test  tb_test(
.clk(clk_50M),
.srst(rst)
);
always #10 clk_50M = ~clk_50M;
endmodule