用Verilog实现九进制波浪计数器
首先,创建新的Verilog文本,打入如下代码
module ligulei7(RST , CLK , CNTVAL);
input RST , CLK ;
output [3:0] CNTVAL;
reg [3:0] CNTVAL;
reg state;
localparam a1 = 1'b0;
localparam a2 = 1'b1;
localparam CNT_MAX_VAL = 9;
always @ (posedge CLK or negedge RST) begin
if(!RST)
CNTVAL <= 0;
else begin
case(state)
a1:if(CNTVAL < CNT_MAX_VAL) begin
CNTVAL <= CNTVAL+1'b1;
state <= a1;
end
else begin
CNTVAL <= CNTVAL-1'b1;
state <= a2;
end
a2:if(CNTVAL == CNT_MAX_VAL) begin
CNTVAL <= CNTVAL-1'b1;
state <= a2;
end
else if(CNTVAL < CNT_MAX_VAL) begin
if(CNTVAL == 0) begin
CNTVAL <= CNTVAL+1'b1;
state <= a1;
end
else begin
CNTVAL <= CNTVAL-1'b1;
state <= a2;
end
end
endcase
end
end
endmodule
之后进行完全编译,建立新的vwf画波形图,得到波形图如下: