【Verilog基础】12.串并转换

4 位串并转换器

module serial_pal(clk,reset,en,in,out);
    input clk,reset,en,in;
    output[3:0] out;
    reg[3:0] out;
    always @(posedge clk)
    begin
        if(reset) out<=4'h0;
        else if(en) out<={out,in}; //使用连接运算符
    end
endmodule

串行输入串行输出

module siso4_1(dout,clk,din);
    output dout; //数据输出端
    input clk,din; //时钟信号、数据输入端
    reg dout;
    reg[3:0] q;
    integer i;
always @(posedge clk)
    begin
         q[0]<=din;
         for(i=0;i<=2;i=i+1)
         begin q[i+1]<=q[i]; end
         dout<=q[3];
    end
endmodule

串行输入并行输出

module sipo(dout,clk,din,clr);
    output[4:0] dout; //输出数据端
    input clk,din,clr; //时钟信号、输入数据端、清零端
    reg[4:0] dout;
always @(posedge clk)
    begin
     if(clr)
     begin dout<=0; end
     else
     begin dout<={dout,din}; end
    end
endmodule

并行输入串行输出

module piso4(dout,clk,clr,din);
    output dout; //数据输出端
    input clk,clr; //时钟信号、清零端
    input[3:0] din; //数据输入端
    reg dout;
    reg[1:0] cnt;
    reg[3:0] q;
always @(posedge clk)
    begin
     cnt<=cnt+1;
     if(clr)
     begin q<=4'b0000; end
     else
     begin 
     if(cnt>0)
     begin q[3:1]<=q[2:0]; end
     else if(cnt==2'b00)
     begin q<=din; end
     end
     dout<=q[3];
    end 
endmodule

串并转换——左移位和右移位实现

module d_reg1(dout_r,dout_l,clk,din,left_right);
    output dout_r,dout_l; //右移输出端、左移输出端
    input clk,din,left_right; //时钟信号、数据输入端、方向控制信号
    reg dout_r,dout_l;
    reg[7:0] q_temp;
    integer i;
always @(posedge clk)
    begin
     if(left_right)
     begin 
         q_temp[7]<=din;
         for(i=7;i>=1;i=i-1) 
         begin q_temp[i-1]<=q_temp[i]; end
     end
     else
     begin
         q_temp[0]<=din;
         for(i=1;i<=7;i=i+1)
         begin q_temp[i]<=q_temp[i-1]; end
         end 
         dout_r<=q_temp[0];
         dout_l<=q_temp[7];
    end
endmodule