程序代码
module top(
input clk, //20Mhz时钟
input rst_n,
input [3:0] key,
output reg [4:0] led
);
//reg define
reg [ 3:0] led_ctrl;
reg [23:0] cnt;
//parameter define
parameter delaytime=24'd1000_0000;// 20Mhz clock delay 0.5m
//延时计数器
always @ (posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<=24'd0;
else
if(cnt < delaytime)
cnt <= cnt + 1'b1;
else
cnt <= 24'd0;
end
//led灯状态寄存器
always @ (posedge clk or negedge rst_n) begin
if(!rst_n)
led_ctrl <= 3'd0;
else
if(cnt == delaytime)
led_ctrl <= led_ctrl + 1'b1;
else if ( led_ctrl == 3'd5)
led_ctrl <= 3'd0;
else
led_ctrl <= led_ctrl;
end
//根据按键来改变LED的状态
always @ (posedge clk or negedge rst_n) begin
if(!rst_n)
led <= 5'b00000;
else
if(key[0]==1'b1)
case(led_ctrl)
3'd0: led <= 5'b11110;
3'd1: led <= 5'b11101;
3'd2: led <= 5'b11011;
3'd3: led <= 5'b10111;
3'd4: led <= 5'b01111;
endcase
else if(key[1]==1'b1)
case(led_ctrl)
3'd0: led <= 5'b01111;
3'd1: led <= 5'b10111;
3'd2: led <= 5'b11011;
3'd3: led <= 5'b11101;
3'd4: led <= 5'b11110;
endcase
else if(key[2]==1'b1)
case(led_ctrl)
3'd0: led <= 5'b00000;
3'd1: led <= 5'b11111;
3'd2: led <= 5'b00000;
3'd3: led <= 5'b11111;
3'd4: led <= 5'b00000;
endcase
else if(key[3]==1'b1)
led <= 5'b00000;
else
led <= 5'b11111;
end
endmodule
测试文件代码
module TD_key_ctl_led;
// Inputs
reg clk;
reg rst_n;
reg [3:0] key;
// Outputs
wire [4:0] led;
parameter delaytime = 26'd10;
// Instantiate the Unit Under Test (UUT)
top #(.delaytime(delaytime)) uut (
.clk(clk),
.rst_n(rst_n),
.key(key),
.led(led)
);
always #20 clk=~clk;//产生20M时钟信号
initial begin
// Initialize Inputs
clk = 0;
rst_n = 0;
// Wait 100 ns for global reset to finish
#20;
rst_n = 1;
key = 4'b1110;
#3000;
rst_n = 0;
#20;
rst_n = 1;
key = 4'b1101;
// Add stimulus here
end
endmodule
ucf
# PlanAhead Generated physical constraints
NET "led[4]" LOC = P12;
NET "led[3]" LOC = P13;
NET "led[2]" LOC = P15;
NET "led[1]" LOC = P16;
NET "led[0]" LOC = P20;
NET "clk" LOC = P86;
NET "rst_n" LOC = P82;
NET "key[3]" LOC = P70;
NET "key[2]" LOC = P71;
NET "key[1]" LOC = P72;
NET "key[0]" LOC = P73;