数码管静态显示

顶层模块代码

`timescale 1ns / 1ps
module segdisplay_top(
	input				sys_clk,
	input 			sys_rst_n,
	
	output	[5:0]	sel,
	output	[7:0]	seg_led
);

parameter	TIME_SHOW = 25'd2500_0000;
wire			add_flag;
 
time_cnt # (.MAX_NUM(TIME_SHOW))u_time_cnt(
	.clk			(sys_clk),
	.rst_n		(sys_rst_n),
	
	.flag			(add_flag)
    );
	 
seg_led_static u_seg_led_static(
	.clk			(sys_clk),
	.rst_n		(sys_rst_n),
	
	.add_flag	(add_flag),
	.sel			(sel),
	.seg_led		(seg_led)
	);

endmodule

子模块代码

`timescale 1ns / 1ps
module time_cnt(
	input				clk,
	input				rst_n,
	
	output	reg	flag
    );
	 
parameter	MAX_NUM = 25000_000; //50Mhz一个时钟周期20ns,延时0.5秒需要25000000个时钟周期
reg	[24:0]	cnt;

always @ (posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		flag <= 1'b0;
		cnt  <= 24'b0;
	end
	else if (cnt < MAX_NUM - 1'b1) begin
		cnt <= cnt +1'b1;
		flag <= 1'b0;
	end
	else begin
		cnt <= 24'b0;
		flag <= 1'b1;
	end
end

endmodule

子模块代吗

`timescale 1ns / 1ps
module seg_led_static(
	input						clk,
	input						rst_n,
	
	input						add_flag,
	output	reg	[5:0]	sel,
	output	reg	[7:0]	seg_led
	);
reg	[3:0]	num;

always @ (posedge clk or negedge rst_n) begin
	if (!rst_n)
		sel <= 6'b111_111;
	else
		sel <= 6'b000_000;//控制所有数码管都处在上电工作状态
end

always @ (posedge clk or negedge rst_n) begin
	if (!rst_n)
		num <= 4'h0;
	else if (add_flag) begin
			if(num < 4'hf)
				num <= num + 1'b1;
			else
				num <= 4'h0;
	end
	else
		num <= num;
end
always @ (posedge clk or negedge rst_n) begin
	if (!rst_n)
		seg_led <= 8'b0;
	else begin
		case (num)
			4'h0 		: 	seg_led <= 8'b1100_0000;
			4'h1 		: 	seg_led <= 8'b1111_1001;
			4'h2 		:	seg_led <= 8'b1010_0100;
			4'h3 		: 	seg_led <= 8'b1011_0000;
			4'h4 		:	seg_led <= 8'b1001_1001;
			4'h5 		: 	seg_led <= 8'b1001_0010;
			4'h6 		:	seg_led <= 8'b1000_0010;
			4'h7 		:	seg_led <= 8'b1111_1000;
			4'h8		:	seg_led <= 8'b1000_0000;
			4'h9 		:	seg_led <= 8'b1001_0000;
			4'ha 		:	seg_led <= 8'b1000_1000;
			4'hb 		:	seg_led <= 8'b1000_0011;
			4'hc 		:	seg_led <= 8'b1100_0110;
			4'hd 		:	seg_led <= 8'b1010_0001;
			4'he 		: 	seg_led <= 8'b1000_0110;
			4'hf		: 	seg_led <= 8'b1000_1110;
			default 	:	seg_led <= 8'b1100_0000;
		endcase
	end
end
endmodule

测试文件

`timescale 1ns / 1ps

module td_segdisplay_top;

	reg	sys_clk;
	reg	sys_rst_n;
	wire	[5:0] sel;
	wire	[7:0] seg_led;
	
	parameter	DELAY_TIME = 25'd10;

	// Instantiate the Unit Under Test (UUT)
	segdisplay_top #(.TIME_SHOW(DELAY_TIME))uut (
		.sys_clk(sys_clk), 
		.sys_rst_n(sys_rst_n), 
		.sel(sel), 
		.seg_led(seg_led)
	);
	//产生时钟信号
	always #10 sys_clk <= ~sys_clk;
	
	initial begin
		// Initialize Inputs
		sys_clk = 0;
		sys_rst_n = 0;
		//simulate code
		#20;
		sys_rst_n = 1;	
	end    
endmodule

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