io vivado 怎么查看ps_把51的7段数码管显示程序移植到ZYNQ上（二）——Vivado下PS和PL的IP集成...

最新推荐文章于 2024-06-18 17:48:31 发布

weixin_39574287

最新推荐文章于 2024-06-18 17:48:31 发布

阅读量205

点赞数

文章标签： io vivado 怎么查看ps

本文链接：https://blog.csdn.net/weixin_39574287/article/details/111548169

版权

咱们接着来，Seg7_Mux的IP设计好之后如果没有拷贝到Vivado的IP目录里面，我们可以直接在IP Catlog添加自己的IP。为了以防万一，我们需要先仿真一下(这是需要照顾一下以前用ISE的同学，由于IP本身已经验证过，这里只是选做而已。如果你已经会做或者只专注于PS端的程序，仿真的步骤可以跳过)：

将添加的Seg7_Mux的端口全部连接到外部(Ctrl+T)

创建一个顶层的HDL Wrapper

添加仿真激励文件

选择激励文件我把代码和文件名贴在下面，不用去理解了，直接新建在项目里添加就行：

TB_Seg7_Mux.vhd文件源代码：

--------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;

use UNISIM.VCOMPONENTS.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY TB_Seg7_Mux IS

END TB_Seg7_Mux;

ARCHITECTURE behavior OF TB_Seg7_Mux IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT design_Seg7_Mux_wrapper

PORT(

Data_Latch : in STD_LOGIC_VECTOR ( 0 to 0 );

Input_data : in STD_LOGIC_VECTOR ( 7 downto 0 );

Output_Data_A : out STD_LOGIC_VECTOR ( 7 downto 0 );

Output_Data_B : out STD_LOGIC_VECTOR ( 7 downto 0 );

Output_Select : out STD_LOGIC_VECTOR ( 7 downto 0 );

Select_Latch : in STD_LOGIC_VECTOR ( 0 to 0 );

ap_clk : in STD_LOGIC;

ap_ctrl_done : out STD_LOGIC;

ap_ctrl_idle : out STD_LOGIC;

ap_ctrl_ready : out STD_LOGIC;

ap_ctrl_start : in STD_LOGIC;

ap_rst : in STD_LOGIC);

END COMPONENT;

--Inputs

signal ap_clk : std_logic := '0';

signal ap_rst : std_logic := '0';

signal ap_ctrl_start : std_logic := '1';

signal Input_data : std_logic_vector(7 downto 0) := (others => '0');

signal Data_Latch : std_logic_vector(0 downto 0) := (others => '0');

signal Select_Latch : std_logic_vector(0 downto 0) := (others => '0');

--Outputs

signal ap_ctrl_done : std_logic;

signal ap_ctrl_idle : std_logic;

signal ap_ctrl_ready : std_logic;

signal Output_Data_A : std_logic_vector(7 downto 0);

signal Output_Data_B : std_logic_vector(7 downto 0);

signal Output_Select : std_logic_vector(7 downto 0);

-- Clock period definitions

constant ap_clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: design_Seg7_Mux_wrapper PORT MAP (

Data_Latch=>Data_Latch,

Input_data=>Input_data,

Output_Data_A=>Output_Data_A,

Output_Data_B=>Output_Data_B,

Output_Select=>Output_Select,

Select_Latch=>Select_Latch,

ap_clk=>ap_clk,

ap_ctrl_done=>ap_ctrl_done,

ap_ctrl_idle=>ap_ctrl_idle,

ap_ctrl_ready=>ap_ctrl_ready,

ap_ctrl_start=>ap_ctrl_start,

ap_rst=>ap_rst

);

-- Clock process definitions

ap_clk_process :process

begin

ap_clk <= '0';

wait for ap_clk_period/2;

ap_clk <= '1';

wait for ap_clk_period/2;

end process;

-- Stimulus process

stim_rst: process

begin

ap_rst<='0';

wait;

end process;

stim_start: process

begin

ap_ctrl_start<='1';

wait;

end process;

stim_Data_Latch: process

begin

Data_Latch<="0";

wait for 1us;

Data_Latch<="1";

wait for 500ns;

Data_Latch<="0";

wait for 1us;

Data_Latch<="0";

wait for 2500ns;

end process;

stim_Select_Latch: process

begin

Select_Latch<="0";

wait for 2500ns;

Select_Latch<="0";

wait for 1us;

Select_Latch<="1";

wait for 500ns;

Select_Latch<="0";

wait for 1us;

end process;

stim_Input_data: process

begin

Input_data<=(others=>'0');

wait for 2500ns;

Input_data<=(others=>'1');

wait for 2500ns;

Input_data<="00111111";

wait for 2500ns;

Input_data<="11111110";

wait for 2500ns;

Input_data<="00000110";

wait for 2500ns;

Input_data<="11111101";

wait for 2500ns;

Input_data<="01011011";

wait for 2500ns;

Input_data<="11111011";

wait for 2500ns;

Input_data<="01001111";

wait for 2500ns;

Input_data<="11110111";

wait for 2500ns;

Input_data<="01100110";

wait for 2500ns;

Input_data<="11101111";

wait for 2500ns;

Input_data<="01101101";

wait for 2500ns;

Input_data<="11011111";

wait for 2500ns;

Input_data<="01111101";

wait for 2500ns;

Input_data<="10111111";

wait for 2500ns;

Input_data<="00000111";

wait for 2500ns;

Input_data<="01111111";

wait for 2500ns;

end process;

END;

选中你的仿真激励文件

开始仿真：

行为仿真结果。

回到块设计框图，除了3个8位输出端口外其他外部端口都删除，然后添加一个PS的IP和三个Slice的IP以及一个Constant进行连接：

完成连接之后验证一下设计，由于已经导入管脚约束文件可以直接生成Bit流文件了。下面把管脚约束文件的源代码和对应的原理图贴出来：

管脚约束文件Seg_Mux.xdc代码如下：

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_A[7]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_A[6]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_A[5]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_A[4]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_A[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_A[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_A[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_A[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_B[7]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_B[6]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_B[5]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_B[4]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_B[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_B[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_B[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Data_B[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Select[7]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Select[6]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Select[5]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Select[4]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Select[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Select[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Select[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {Output_Select[0]}]

set_property PACKAGE_PIN W8 [get_ports {Output_Select[7]}]

set_property PACKAGE_PIN AB6 [get_ports {Output_Select[6]}]

set_property PACKAGE_PIN AB5 [get_ports {Output_Select[5]}]

set_property PACKAGE_PIN AA4 [get_ports {Output_Select[4]}]

set_property PACKAGE_PIN U11 [get_ports {Output_Select[3]}]

set_property PACKAGE_PIN W10 [get_ports {Output_Select[2]}]

set_property PACKAGE_PIN V7 [get_ports {Output_Select[1]}]

set_property PACKAGE_PIN Y9 [get_ports {Output_Select[0]}]

set_property PACKAGE_PIN V5 [get_ports {Output_Data_B[7]}]

set_property PACKAGE_PIN Y5 [get_ports {Output_Data_B[6]}]

set_property PACKAGE_PIN W5 [get_ports {Output_Data_B[5]}]

set_property PACKAGE_PIN W7 [get_ports {Output_Data_B[4]}]

set_property PACKAGE_PIN W6 [get_ports {Output_Data_B[3]}]

set_property PACKAGE_PIN AA6 [get_ports {Output_Data_B[2]}]

set_property PACKAGE_PIN AB4 [get_ports {Output_Data_B[1]}]

set_property PACKAGE_PIN Y6 [get_ports {Output_Data_B[0]}]

set_property PACKAGE_PIN AA8 [get_ports {Output_Data_A[7]}]

set_property PACKAGE_PIN V9 [get_ports {Output_Data_A[6]}]

set_property PACKAGE_PIN W11 [get_ports {Output_Data_A[5]}]

set_property PACKAGE_PIN V14 [get_ports {Output_Data_A[4]}]

set_property PACKAGE_PIN U12 [get_ports {Output_Data_A[3]}]

set_property PACKAGE_PIN AA7 [get_ports {Output_Data_A[2]}]

set_property PACKAGE_PIN Y10 [get_ports {Output_Data_A[1]}]

set_property PACKAGE_PIN V10 [get_ports {Output_Data_A[0]}]