android存储挂载点总线,Cortex-M3 DesignStart AHB总线上挂载存储模块

359module AHB2MEM

360 #(parameter MEMWIDTH = 15) // Size = 32KB

361 (

362 input wire HSEL,

363 input wire HCLK,

364 input wire HRESETn,

365 input wire HREADY,

366 input wire [31:0] HADDR,

367 input wire [1:0] HTRANS,

368 input wire HWRITE,

369 input wire [2:0] HSIZE,

370 input wire [31:0] HWDATA,

371 output wire HREADYOUT,

372 output reg [31:0] HRDATA

373 );

374

375 assign HREADYOUT = 1'b1; // Always ready

376

377 // Memory Array

378 reg [31:0] memory[0:(2**(MEMWIDTH-2)-1)];

379

380 // Registers to store Adress Phase Signals

381 reg [31:0] hwdata_mask;

382 reg we;

383 reg [31:0] buf_hwaddr;

384

385 // Sample the Address Phase

386 always @(posedge HCLK or negedge HRESETn)

387 begin

388 if(!HRESETn)

389 begin

390 we <= 1'b0;

391 buf_hwaddr <= 32'h0;

392 end

393 else

394 if(HREADY)

395 begin

396 we <= HSEL & HWRITE & HTRANS[1];

397 buf_hwaddr <= HADDR;

398

399 casez (HSIZE[1:0])

400 2'b1?: hwdata_mask <= 32'hFFFFFFFF; // Word write

401 2'b01: hwdata_mask <= (32'h0000FFFF << (16 * HADDR[1])); // Halfword write

402 2'b00: hwdata_mask <= (32'h000000FF << (8 * HADDR[1:0])); // Byte write

403 endcase

404 end

405 end

406

407 // Read and Write Memory

408 always @ (posedge HCLK)

409 begin

410 if(we)

411 memory[buf_hwaddr[MEMWIDTH:2]] <= (HWDATA & hwdata_mask) | (HRDATA & ~hwdata_mask);

412 HRDATA = memory[HADDR[MEMWIDTH:2]];

413 end

414

415endmodule