verilog写操作查询表_电子表的设计——verilog

电子表的设计包括正常计时模块，LED显示模块，定时报警模块，校时模块，秒表模块。

(1)正常计时模块clock

module

clock(clk,rst,clock_en,second,minute,hour);

input clk,rst,clock_en;

output[5:0]second,minute,hour;

reg[5:0]second,minute,hour;

always@(posedge clk or negedge rst or posedge

clock_en)

if(!rst)

begin

second<=0; minute<=0; hour<=0;

end

else if(clock_en)

begin

if(second==59)

begin

minute<=minute+1;

second<=0;

end

else if(minute==59)

begin

hour<=hour+1;

minute<=0;

end

else if(hour==23)

hour<=0;

else

second<=second+1;

end

endmodule

(2)LED显示模块LED_display

module

LED_display(data,high,low);

input[5:0]data;

output[7:0]high,low;

reg[7:0]high,low;

reg[3:0]out_h,out_l;

begin

out_h<=data/10;

out_l<=data;

end

always@(out_l)

case(out_l)

4'b0000:low<=8'b00000000;

4'b0001:low<=8'b01100000;

4'b0010:low<=8'b11011010;

4'b0011:low<=8'b11110010;

4'b0100:low<=8'b01100110;

4'b0101:low<=