Verilog专题（十八）3输入的查找表（LUT）

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题目

First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7]. The shift register input should be called S, which feeds the input of Q[0] (MSB is shifted in first). The enable input controls whether to shift. Then, extend the circuit to have 3 additional inputs A,B,C and an output Z. The circuit's behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. (Aside: this circuit is called a 3-input look-up-table (LUT)).

 

我的设计

    根据题目的要求，LUT是由一个8选1的MUX和一个左移移位寄存器组成，注意的是8选1的MUX我用了一个比较简洁的写法（第12行），当然也可以用always中的case语句去完成，效果一样，代码如下：

module top_module (  input clk,  input enable,